A Low Power Embedded DRAM Macro for Battery-Operated LSIs

Takeshi FUJINO; Akira YAMAZAKI; Yasuhiko TAITO; Mitsuya KINOSHITA; Fukashi MORISHITA; Teruhiko AMANO; Masaru HARAGUCHI; Makoto HATAKENAKA; Atsushi AMO; Atsushi HACHISUKA; Kazutami ARIMOTO; Hideyuki OZAKI

A Low Power Embedded DRAM Macro for Battery-Operated LSIs

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A low power 16 Mb embedded DRAM (eDRAM) macro is fabricated using 0.15 µm logic -based embedded DRAM process technology. A 0.5 µm² CUB (apacitor nder it-line) DRAM cell is newly developed for this process. Novel start-up and dynamic fuse-data loading circuit are developed to realize easy customization of memory capacities with minimum area penalty. A new write-mask control circuit using write-gate sense-amplifier is adopted in order to apply column shift-redundancy circuit. Various low power technologies including unique "non-precharge read-data bus" method are applied. In the test-chip adopting new process-technology and three original circuit-design techniques, random column operation of 166 MHz and data retention power of 123 µW are demonstrated at 1.5 V power supply.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E86-A No.12 pp.2991-3000

Publication Date: 2003/12/01

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Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)

Category: Power Optimization

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Takeshi FUJINO, Akira YAMAZAKI, Yasuhiko TAITO, Mitsuya KINOSHITA, Fukashi MORISHITA, Teruhiko AMANO, Masaru HARAGUCHI, Makoto HATAKENAKA, Atsushi AMO, Atsushi HACHISUKA, Kazutami ARIMOTO, Hideyuki OZAKI, "A Low Power Embedded DRAM Macro for Battery-Operated LSIs" in IEICE TRANSACTIONS on Fundamentals, vol. E86-A, no. 12, pp. 2991-3000, December 2003, doi: .
Abstract: A low power 16 Mb embedded DRAM (eDRAM) macro is fabricated using 0.15 µm logic -based embedded DRAM process technology. A 0.5 µm² CUB (apacitor nder it-line) DRAM cell is newly developed for this process. Novel start-up and dynamic fuse-data loading circuit are developed to realize easy customization of memory capacities with minimum area penalty. A new write-mask control circuit using write-gate sense-amplifier is adopted in order to apply column shift-redundancy circuit. Various low power technologies including unique "non-precharge read-data bus" method are applied. In the test-chip adopting new process-technology and three original circuit-design techniques, random column operation of 166 MHz and data retention power of 123 µW are demonstrated at 1.5 V power supply.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e86-a_12_2991/_p

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@ARTICLE{e86-a_12_2991,
author={Takeshi FUJINO, Akira YAMAZAKI, Yasuhiko TAITO, Mitsuya KINOSHITA, Fukashi MORISHITA, Teruhiko AMANO, Masaru HARAGUCHI, Makoto HATAKENAKA, Atsushi AMO, Atsushi HACHISUKA, Kazutami ARIMOTO, Hideyuki OZAKI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A Low Power Embedded DRAM Macro for Battery-Operated LSIs},
year={2003},
volume={E86-A},
number={12},
pages={2991-3000},
abstract={A low power 16 Mb embedded DRAM (eDRAM) macro is fabricated using 0.15 µm logic -based embedded DRAM process technology. A 0.5 µm² CUB (apacitor nder it-line) DRAM cell is newly developed for this process. Novel start-up and dynamic fuse-data loading circuit are developed to realize easy customization of memory capacities with minimum area penalty. A new write-mask control circuit using write-gate sense-amplifier is adopted in order to apply column shift-redundancy circuit. Various low power technologies including unique "non-precharge read-data bus" method are applied. In the test-chip adopting new process-technology and three original circuit-design techniques, random column operation of 166 MHz and data retention power of 123 µW are demonstrated at 1.5 V power supply.},
keywords={},
doi={},
ISSN={},
month={December},}

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TY - JOUR
TI - A Low Power Embedded DRAM Macro for Battery-Operated LSIs
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2991
EP - 3000
AU - Takeshi FUJINO
AU - Akira YAMAZAKI
AU - Yasuhiko TAITO
AU - Mitsuya KINOSHITA
AU - Fukashi MORISHITA
AU - Teruhiko AMANO
AU - Masaru HARAGUCHI
AU - Makoto HATAKENAKA
AU - Atsushi AMO
AU - Atsushi HACHISUKA
AU - Kazutami ARIMOTO
AU - Hideyuki OZAKI
PY - 2003
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E86-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2003
AB - A low power 16 Mb embedded DRAM (eDRAM) macro is fabricated using 0.15 µm logic -based embedded DRAM process technology. A 0.5 µm² CUB (apacitor nder it-line) DRAM cell is newly developed for this process. Novel start-up and dynamic fuse-data loading circuit are developed to realize easy customization of memory capacities with minimum area penalty. A new write-mask control circuit using write-gate sense-amplifier is adopted in order to apply column shift-redundancy circuit. Various low power technologies including unique "non-precharge read-data bus" method are applied. In the test-chip adopting new process-technology and three original circuit-design techniques, random column operation of 166 MHz and data retention power of 123 µW are demonstrated at 1.5 V power supply.
ER -