IEICE TRANSACTIONS on Electronics
A 0.18 µm 32 Mb Embedded DRAM Macro for 3-D Graphics Controller
Summary :
A 23.3 mm2 32 Mb embedded DRAM (eDRAM) macro has been fabricated using 0.18 µm triple-well 4-metal embedded DRAM process technology to realize an accelerated 3-D graphics controller. The array architecture, using a dual-port sense amplifier, achieves the column access latency of two cycles at 222 MHz and a peak data rate of 14.2
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E85-C No.9 pp.1697-1708
- Publication Date
- 2002/09/01
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- PAPER
- Category
- Electronic Circuits
Authors
Akira YAMAZAKI
Takeshi FUJINO
Kazunari INOUE
Isamu HAYASHI
Hideyuki NODA
Naoya WATANABE
Fukashi MORISHITA
Katsumi DOSAKA
Yoshikazu MOROOKA
Shinya SOEDA
Kazutami ARIMOTO
Setsuo WAKE
Kazuyasu FUJISHIMA
Hideyuki OZAKI
Keyword
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Akira YAMAZAKI, Takeshi FUJINO, Kazunari INOUE, Isamu HAYASHI, Hideyuki NODA, Naoya WATANABE, Fukashi MORISHITA, Katsumi DOSAKA, Yoshikazu MOROOKA, Shinya SOEDA, Kazutami ARIMOTO, Setsuo WAKE, Kazuyasu FUJISHIMA, Hideyuki OZAKI, "A 0.18 µm 32 Mb Embedded DRAM Macro for 3-D Graphics Controller" in IEICE TRANSACTIONS on Electronics,
vol. E85-C, no. 9, pp. 1697-1708, September 2002, doi: .
Abstract: A 23.3 mm2 32 Mb embedded DRAM (eDRAM) macro has been fabricated using 0.18 µm triple-well 4-metal embedded DRAM process technology to realize an accelerated 3-D graphics controller. The array architecture, using a dual-port sense amplifier, achieves the column access latency of two cycles at 222 MHz and a peak data rate of 14.2
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e85-c_9_1697/_p
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@ARTICLE{e85-c_9_1697,
author={Akira YAMAZAKI, Takeshi FUJINO, Kazunari INOUE, Isamu HAYASHI, Hideyuki NODA, Naoya WATANABE, Fukashi MORISHITA, Katsumi DOSAKA, Yoshikazu MOROOKA, Shinya SOEDA, Kazutami ARIMOTO, Setsuo WAKE, Kazuyasu FUJISHIMA, Hideyuki OZAKI, },
journal={IEICE TRANSACTIONS on Electronics},
title={A 0.18 µm 32 Mb Embedded DRAM Macro for 3-D Graphics Controller},
year={2002},
volume={E85-C},
number={9},
pages={1697-1708},
abstract={A 23.3 mm2 32 Mb embedded DRAM (eDRAM) macro has been fabricated using 0.18 µm triple-well 4-metal embedded DRAM process technology to realize an accelerated 3-D graphics controller. The array architecture, using a dual-port sense amplifier, achieves the column access latency of two cycles at 222 MHz and a peak data rate of 14.2
keywords={},
doi={},
ISSN={},
month={September},}
Copy
TY - JOUR
TI - A 0.18 µm 32 Mb Embedded DRAM Macro for 3-D Graphics Controller
T2 - IEICE TRANSACTIONS on Electronics
SP - 1697
EP - 1708
AU - Akira YAMAZAKI
AU - Takeshi FUJINO
AU - Kazunari INOUE
AU - Isamu HAYASHI
AU - Hideyuki NODA
AU - Naoya WATANABE
AU - Fukashi MORISHITA
AU - Katsumi DOSAKA
AU - Yoshikazu MOROOKA
AU - Shinya SOEDA
AU - Kazutami ARIMOTO
AU - Setsuo WAKE
AU - Kazuyasu FUJISHIMA
AU - Hideyuki OZAKI
PY - 2002
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E85-C
IS - 9
JA - IEICE TRANSACTIONS on Electronics
Y1 - September 2002
AB - A 23.3 mm2 32 Mb embedded DRAM (eDRAM) macro has been fabricated using 0.18 µm triple-well 4-metal embedded DRAM process technology to realize an accelerated 3-D graphics controller. The array architecture, using a dual-port sense amplifier, achieves the column access latency of two cycles at 222 MHz and a peak data rate of 14.2
ER -
English
