Transition coverage has been proposed as a measure of two-pattern test capabilities of TPG circuits for use in BIST. This paper investigates experimentally the relationships between transition coverages and actual stuck-open fault coverages in order to reveal what kind of circuits are appropriate for two-pattern testing. Fault simulation was performed using conventional (n-stage) LFSR, 2n-stage LFSR, and one-dimensional cellular automata (CAs) as TPG circuits and such sample circuits as balanced NAND tree and some ISCAS '85 benchmark circuits as CUTs. It was found that CAs which are designed so as to apply exhaustive transitions to any 3-dimensional subspaces can detect high rate of stuck-open faults. Influence of hazards of decreasing the fault coverage is also mentioned.

The difficulties of test generation and test application for VLSI chips have made the built-in self testing attractive. In the scheme, exhaustive or random test patterns are usually applied for logic blocks. However, for the testing of a multiple-output combinational circuit of which outputs depend only on partial input lines, the application of all input patterns may not be necessary in order to exercise the whole circuit. This paper proposes methods of evaluating the length of test sequences that can provide almost exhaustive test patterns to those output-wise subcircuits. Conventional linear feedback shift registers are used as the test pattern generator. Characteristics of pseudorandom sequence and truly random sequence as well are studied, in order to make the difference clear. the probabilities of achieving complete exhaustive testing are also estimated by simulation, showing the validity of the probabilistic model of LFSR sequence. It is shown that the probabilistic approach is effective compared with other deterministic ones.

One-dimensional Cellular Automata (CA's) are considered as potential pseudorandom pattern generators to generate highly random parallel patterns with simple hardware configurations. A class of linear, binary, and of nearest neighbor (radius = 1) CA's is referred to here as elementary ones. This paper investigates operations of such CA's with fixed boundary conditions when non-null boundary values are applied to them. By modifying transition matrices of elementary CA's to include the influence of boundary values, structures of state transition diagrams are determined.

A method to analyze two-pattern test capabilities of autonomous test pattern generator (TPG) circuits for use in built-in self-testing are described. The TPG circuits considered here include arbitrary autonomous linear sequential circuits in which outputs are directly fed out from delay elements. Based on the transition matrix of a circuit, it is shown that the number of distinct transitions in a subspace of state variables can be obtained from rank of the submatrix. The two-pattern test capabilities of LFSRs, cellular automata, and their fast parallel implementation are investigated using the transition coverage as a metric. The relationships with dual circuits and reciprocal circuits are also mentioned.

A method to design one-dimensional cellular arrays to be used as TPG circuits of BIST is described. The interconnections between cells are not limited to adjacent ones but allowed to some neighbors. Completely regular structures that have full-transition coverages for every k-dimensional subspace of state variables are first shown. Then, almost regular arrays which can operate on maximum cycles are derived based on fast parallel implementations of LFSRs.

Cellular automata (CA) implementations are expected as potential test-pattern generators (TPGs) for Built-In Self-Testing of VLSI circuits, in which highly random parallel patterns ought to be generated with simple hardware. Objective here is to design one-dimensional, binary, and linear CA implementations with cyclic boundary conditions that can operate on maximum length of period. To provide maximum period of operations, it is necessary to bring some irregularities into the configurations. It is also expected for TPGs to make maximum or sufficiently long period of operations to prevent re-initialization. Our approach is to generate transition matrices based on fast parallel implementations of LFSRs which have trinomials as characteristic polynomials and then to modify the diagonal components. Some notable properties of diagonal vectors were observed.

Signature analysis using a Multiple-Input LFSR as the output response compaction circuit is widely adopted in actual BIST schemes. While aliasing probabilities for random errors are usually very small, MI-LFSRs are tend to fail detecting diagonal errors. A spot error, which include the diagonal error as a particular case, is defined as multiple bit crrors adjacent in space and in time domain. Then, shuffling of interconnection between CUT output and MI-LFSR input is studied as a scheme to prevent aliasing for such errors. The condition for preventing aliasing due to a predetermined size of single spot error is shown. Block based shuffling and the shortened one are proposed to realize required distance properties. Effect of shuffling for multiple spot errors is examined by simulation showing that shuffling is effective also for a certain extend of multiple spot errors.