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[Author] Teruhiko YAMADA(3hit)

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  • SIFLAP-G: A Method of Diagnosing Gate-Level Faults in Combinational Circuits

    Koji YAMAZAKI  Teruhiko YAMADA  

     
    PAPER

      Vol:
    E76-D No:7
      Page(s):
    826-831

    We propose a method of diagnosing any logical fault in combinational circuits through a repetition of the single fault-net location procedure with the aid of probing, called SIFLAP-G. The basic idea of the method has been obtained through an observation that a single error generated on a fault-net often propagates to primary outputs under an individual test even though multiple fault-nets exist in the circuit under test. Therefore, candidates for each fault-net are first deduced by the erroneous path tracing under the single fault-net assumption and then the fault-net is found out of those candidates by probing. Probing internal nets is done only for some of the candidates, so that it is possible to greatly decrease the number of nets to be probed. Experimental results show that the number seems nearly proportional to the number of fault-nets (about 35 internal nets per fault-net), but almost independent of the type of faults and the circuit size.

  • A Single Bridging Fault Location Technique for CMOS Combinational Circuits

    Koji YAMAZAKI  Teruhiko YAMADA  

     
    PAPER

      Vol:
    E78-D No:7
      Page(s):
    817-821

    A single bridging fault location technique for CMOS combinational circuits is proposed. In this technique, the cause of an error observed at the primary outputs in deduced using a diagnosis table constructed from the circuit under test and the given tests. The size of a diagnosis table is [the number of gates][the number of tests]2 bits, which is much smaller than that of the fault dictionary. The experimental results show that the number of possible bridging faults is reduced to less than 5 in several seconds, when using the tests to detect single stuck-at faults and considering only the bridging faults between physically adjacent nets.

  • On Testing of Josephson Logic Circuits Composed of the 4JL Gates

    Teruhiko YAMADA  Tsuyoshi SASAKI  

     
    LETTER

      Vol:
    E81-D No:7
      Page(s):
    749-752

    We have specified typical fabrication defects of the current injection logic gates with four Josephson junctions (4JL gates), and then investigated the voltage and current behavior of defective gates by SPICE simulation to evaluate the defect coverage achieved by logic testing and current testing. The simulation results show that current testing may possibly achieve a high defect coverage while logic testing cannot detect almost half defects.