IEICE TRANSACTIONS on Information
A Single Bridging Fault Location Technique for CMOS Combinational Circuits
Summary :
A single bridging fault location technique for CMOS combinational circuits is proposed. In this technique, the cause of an error observed at the primary outputs in deduced using a diagnosis table constructed from the circuit under test and the given tests. The size of a diagnosis table is [the number of gates]
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- IEICE TRANSACTIONS on Information Vol.E78-D No.7 pp.817-821
- Publication Date
- 1995/07/25
- Publicized
- Online ISSN
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- Type of Manuscript
- Special Section PAPER (Special Issue on Verification, Test and Diagnosis of VLSI Systems)
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Koji YAMAZAKI, Teruhiko YAMADA, "A Single Bridging Fault Location Technique for CMOS Combinational Circuits" in IEICE TRANSACTIONS on Information,
vol. E78-D, no. 7, pp. 817-821, July 1995, doi: .
Abstract: A single bridging fault location technique for CMOS combinational circuits is proposed. In this technique, the cause of an error observed at the primary outputs in deduced using a diagnosis table constructed from the circuit under test and the given tests. The size of a diagnosis table is [the number of gates]
URL: https://global.ieice.org/en_transactions/information/10.1587/e78-d_7_817/_p
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@ARTICLE{e78-d_7_817,
author={Koji YAMAZAKI, Teruhiko YAMADA, },
journal={IEICE TRANSACTIONS on Information},
title={A Single Bridging Fault Location Technique for CMOS Combinational Circuits},
year={1995},
volume={E78-D},
number={7},
pages={817-821},
abstract={A single bridging fault location technique for CMOS combinational circuits is proposed. In this technique, the cause of an error observed at the primary outputs in deduced using a diagnosis table constructed from the circuit under test and the given tests. The size of a diagnosis table is [the number of gates]
keywords={},
doi={},
ISSN={},
month={July},}
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TY - JOUR
TI - A Single Bridging Fault Location Technique for CMOS Combinational Circuits
T2 - IEICE TRANSACTIONS on Information
SP - 817
EP - 821
AU - Koji YAMAZAKI
AU - Teruhiko YAMADA
PY - 1995
DO -
JO - IEICE TRANSACTIONS on Information
SN -
VL - E78-D
IS - 7
JA - IEICE TRANSACTIONS on Information
Y1 - July 1995
AB - A single bridging fault location technique for CMOS combinational circuits is proposed. In this technique, the cause of an error observed at the primary outputs in deduced using a diagnosis table constructed from the circuit under test and the given tests. The size of a diagnosis table is [the number of gates]
ER -
English
