SIFLAP-G: A Method of Diagnosing Gate-Level Faults in Combinational Circuits

Koji YAMAZAKI; Teruhiko YAMADA

SIFLAP-G: A Method of Diagnosing Gate-Level Faults in Combinational Circuits

Koji YAMAZAKI, Teruhiko YAMADA

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We propose a method of diagnosing any logical fault in combinational circuits through a repetition of the single fault-net location procedure with the aid of probing, called SIFLAP-G. The basic idea of the method has been obtained through an observation that a single error generated on a fault-net often propagates to primary outputs under an individual test even though multiple fault-nets exist in the circuit under test. Therefore, candidates for each fault-net are first deduced by the erroneous path tracing under the single fault-net assumption and then the fault-net is found out of those candidates by probing. Probing internal nets is done only for some of the candidates, so that it is possible to greatly decrease the number of nets to be probed. Experimental results show that the number seems nearly proportional to the number of fault-nets (about 35 internal nets per fault-net), but almost independent of the type of faults and the circuit size.

Publication: IEICE TRANSACTIONS on Information Vol.E76-D No.7 pp.826-831

Publication Date: 1993/07/25

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Type of Manuscript: Special Section PAPER (Special Issue on VLSI Testing and Testable Design)

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Koji YAMAZAKI, Teruhiko YAMADA, "SIFLAP-G: A Method of Diagnosing Gate-Level Faults in Combinational Circuits" in IEICE TRANSACTIONS on Information, vol. E76-D, no. 7, pp. 826-831, July 1993, doi: .
Abstract: We propose a method of diagnosing any logical fault in combinational circuits through a repetition of the single fault-net location procedure with the aid of probing, called SIFLAP-G. The basic idea of the method has been obtained through an observation that a single error generated on a fault-net often propagates to primary outputs under an individual test even though multiple fault-nets exist in the circuit under test. Therefore, candidates for each fault-net are first deduced by the erroneous path tracing under the single fault-net assumption and then the fault-net is found out of those candidates by probing. Probing internal nets is done only for some of the candidates, so that it is possible to greatly decrease the number of nets to be probed. Experimental results show that the number seems nearly proportional to the number of fault-nets (about 35 internal nets per fault-net), but almost independent of the type of faults and the circuit size.
URL: https://global.ieice.org/en_transactions/information/10.1587/e76-d_7_826/_p

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@ARTICLE{e76-d_7_826,
author={Koji YAMAZAKI, Teruhiko YAMADA, },
journal={IEICE TRANSACTIONS on Information},
title={SIFLAP-G: A Method of Diagnosing Gate-Level Faults in Combinational Circuits},
year={1993},
volume={E76-D},
number={7},
pages={826-831},
abstract={We propose a method of diagnosing any logical fault in combinational circuits through a repetition of the single fault-net location procedure with the aid of probing, called SIFLAP-G. The basic idea of the method has been obtained through an observation that a single error generated on a fault-net often propagates to primary outputs under an individual test even though multiple fault-nets exist in the circuit under test. Therefore, candidates for each fault-net are first deduced by the erroneous path tracing under the single fault-net assumption and then the fault-net is found out of those candidates by probing. Probing internal nets is done only for some of the candidates, so that it is possible to greatly decrease the number of nets to be probed. Experimental results show that the number seems nearly proportional to the number of fault-nets (about 35 internal nets per fault-net), but almost independent of the type of faults and the circuit size.},
keywords={},
doi={},
ISSN={},
month={July},}

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TY - JOUR
TI - SIFLAP-G: A Method of Diagnosing Gate-Level Faults in Combinational Circuits
T2 - IEICE TRANSACTIONS on Information
SP - 826
EP - 831
AU - Koji YAMAZAKI
AU - Teruhiko YAMADA
PY - 1993
DO -
JO - IEICE TRANSACTIONS on Information
SN -
VL - E76-D
IS - 7
JA - IEICE TRANSACTIONS on Information
Y1 - July 1993
AB - We propose a method of diagnosing any logical fault in combinational circuits through a repetition of the single fault-net location procedure with the aid of probing, called SIFLAP-G. The basic idea of the method has been obtained through an observation that a single error generated on a fault-net often propagates to primary outputs under an individual test even though multiple fault-nets exist in the circuit under test. Therefore, candidates for each fault-net are first deduced by the erroneous path tracing under the single fault-net assumption and then the fault-net is found out of those candidates by probing. Probing internal nets is done only for some of the candidates, so that it is possible to greatly decrease the number of nets to be probed. Experimental results show that the number seems nearly proportional to the number of fault-nets (about 35 internal nets per fault-net), but almost independent of the type of faults and the circuit size.
ER -