This paper describes a high-power and low-distortion AlGaAs/GaAs HFET amplifier developed for digital cellular base station system. We proved experimentally that distortion characteristics such as IMD (Intermodulation Distortion) or NPR (Noise Power Ratio) are drastically degraded when the absolute value of the drain bias circuit impedance at low frequency are high. Based on the experimental results, we have designed the drain bias circuit not to influence the distortion characteristics. The developed amplifier employed two pairs of pre-matched GaAs chips mounted on a single package and the total output-power was combined in push-pull configuration with a microstrip balun circuit. The push-pull amplifier demonstrated state-of-the-art performance of 140 W output-power with 11.5 dB linear gain at 2.2 GHz. In addition, it exhibited extremely low distortion performance of less than 30 dBc at two-tone total output-power of 46 dBm. These results indicate that the design of the drain bias circuit is of great importance to achieve improved IMD characteristics while maintaining high power performance.

A neuron-MOS transistor (νMOS) is applied to current-mode multi-valued logic (MVL) circuits. First, a novel low-voltage and low-power νMOS current mirror is presented. Then, a threshold detector and a quaternary T-gate using the proposed νMOS current mirrors are proposed. The minimum output voltage of the νMOS current mirror is decreased by VT (threshold voltage), compared with the conventional double cascode current mirror. The νMOS threshold detector is built on a νMOS current comparator originally composed of νMOS current mirrors. It has a high output swing and sharp transfer characteristics. The gradient of the proposed comparator output in the transfer region can be increased 6.3-fold compared with that in the conventional comparator. Along with improved operation of the novel current comparator, the discriminative ability of the proposed νMOS threshold detector is also increased. The performances of the proposed circuits are validated by HSPICE with Motorola 1.5 µm CMOS device parameters. Furthermore, the operation of a νMOS current mirror is also confirmed through experiments on test chips fabricated by VDEC*. The active area of the proposed νMOS current mirror is 63 µm 51 µm.

This paper presents a new approach to designing arithmetic circuits by using a graph-based evolutionary optimization technique called Evolutionary Graph Generation (EGG). The key idea of the proposed method is to introduce a higher level of abstraction for arithmetic algorithms, in which arithmetic circuit structures are modeled as data-flow graphs associated with specific number representation systems. The EGG system employs evolutionary operations to transform the structure of graphs directly, which makes it possible to generate the desired circuit structure efficiently. The potential capability of EGG is demonstrated through an experiment of generating constant-coefficient multipliers.

An on-chip high voltage generator applicable to low voltage flash memory is introduced. Bootstrapped gate transfer switches of two parallel paths suppress the voltage loss due to threshold voltage drop of transfer transistors. The simulated results demonstrate that proposed circuit designed with NMOS transistors having 0.8 volt threshold voltage works like an ideal charge pump circuit near 1.0 volt range with enough current driving capability.

In this paper, a four-quadrant analog multiplier consisting of four neuron-MOS transistors and two load resistors is proposed. The proposed multiplier can be operated at only 1 V. Furthermore, the input range of the multiplier is equal to 100% of the supply voltage. The theoretical harmonic distortion caused by mobility degradation and device mismatchs is derived in detail. The performance of the proposed multiplier is characterized through HSPICE simulations with a standard 2.0 µm CMOS process with a double-poly layer. Simulations of the proposed multiplier demonstrate that the linearity error of 0.77% and a total harmonic distortion of 0.62% are obtained with full-scale input conditions. The maximum power consumption and 3 dB bandwidth are 9.56 µW and 107 MHz, respectively. The active area of the proposed multiplier is 210 µm 140 µm.

This paper presents a novel distortion compensation technique using an active inductor. First, we describe the input-reflection-coefficient characteristics of a GaAs MESFET active inductor when input power increases. We show that the inductor exhibits positive amplitude deviation and negative/positive phase deviation as the input power increases when the biases of the FETs are set appropriately. The chip size of the fabricated active inductor is less than 0.52 mm2. Then, we show that third-order intermodulation is improved when the active inductor is used as a predistortion linearizer. Third-order intermodulation was improved over the output range from 14 dBm to 25 dBm, and at the output of 15 dBm, third-order intermodulation was improved approximately by 9 dB when the predistortion linearizer was introduced. The active inductor can thus function as a miniaturized predistortion linearizer by using it in the input matching circuit of a power amplifier. This technique can be applied in the miniaturization of wireless communication devices.

We show that the permanent of an m n rectangular matrix can be computed with O(n 2m 3m) multiplications and additions. Asymptotically, this is better than straightforward extensions of the best known algorithms for the permanent of a square matrix when m/n log3 2 and n .

We proposed Reversible Energy Recovery Logic (RERL) using an 8-phase clocking scheme, which is a dual-rail reversible adiabatic logic for ultra-low-energy applications. Because we eliminated non-adiabatic energy loss in RERL by using the concept of reversible logic, RERL has only adiabatic and leakage losses. In this paper we explain its operation and logic design and present its simulation and experimental results. We also present an energy-efficient 8-phase, clocked power generator that uses an off-chip inductor. With simulation results for the full adder, we confirmed that the RERL circuit consumed substantially less energy than other logic circuits at low-speed operation. We evaluated a test chip implemented with a 0.6-µm CMOS technology, which integrated a chain of inverters with a clocked power generator. In the experimental results, the RERL circuit consumed only 4.5% of the dissipated energy of a static CMOS circuit at an optimal operating speed of 40 kHz. In conclusion, RERL is suitable for the applications that do not require high performance but low-energy consumption because its energy consumption can be decreased to the minimum by reducing the operating frequency until adiabatic and leakage losses are equal.

A model of the prefrontal cortical circuit has been constructed to investigate the dynamics for working memory processing. The model circuit is multi-layered and consists of a number of circuit modules or columns, each of which has local, excitatory and inhibitory connections as well as feedback connections. The columns interact with each other via the long-range horizontal connections. Besides these intrinsic connections, the pyramidal and spiny cells in the superficial layers receive the specific cue-related input and all the cortical neurons receive a hypothetical bias input. The model cortical circuit amplifies the response to the transient, cue-related input. The dynamics of the circuit evolves autonomously after the termination of the input. As a result, the circuit reaches in several hundred milliseconds an equilibrium state, in which the neurons exhibit graded-level, sustained activity. The sustained activity varies gradually with the cue direction, thus forming memory fields. In the formation of the memory fields, the feedback connections, the horizontal connections, and the bias input all play important roles. Varying the level of the bias input dramatically changes the dynamics of the model cortical neurons. The computer simulations show that there is an optimum level of the input for the formation of well-defined memory fields during the delay period.

This paper is consisting of the two novel EMC technologies that we have been developed in our laboratory. The first is the technology for measuring the RF (Radio Frequency) nearby magnetic field and estimation of the RF current in the printed circuit board (PCB) by using the small loop antenna with multi-layer PCB structure developed by our laboratory. I introduce the application of our small loop antenna with its physical structure and the analysis of the nearby magnetic field distribution of the printed circuit board applying the discrete Wavelet analysis. We can understand the behavior of the digital circuit in detail, and we can also take measures to meet the specification about the electromagnetic radiation from the digital circuit from the higher order of priority by using these technologies. The second is our proposing novel technology for reducing the electromagnetic radiation from the digital equipment by taking notice of the improvement of the de-coupling in the PCB. We confirmed the remarkable effect of this technology by redesigning the motherboard of the small-sized computer.

The clock recovery circuit is a key component in high-speed electrical time-division multiplexing (ETDM) transmission systems. In the case of clock extraction from non-return-to-zero (NRZ) signals, differentiation and full-wave rectification are indispensable. Exclusive OR/NOR circuits (XOR) are widely used for this purpose. In this paper, we describe an XOR IC fabricated with 0. 1-µm gate-length InAlAs/InGaAs/InP HEMTs for a 40-Gbit/s class clock recovery circuit. The IC was configured with a symmetrical Gilbert cell type XOR gate and two types of peaking techniques are used to achieve its high bit-rate. On-wafer-measurements indicate that the IC operates as fast as 80 Gbit/s and can extract a 40-GHz frequency component from 40-Gbit/s NRZ input signals. To confirm the feasibility of using the packaged XOR IC in clock recovery circuits, the conversion gain of the IC, which was operated as a differentiater and full-wave rectifier, was evaluated. Assuming that the input to the clock recovery circuit is a 1 Vp-p signal, the relatively high output power of -17 dBm can be obtained with low dependency on the length of the input pseudo-random bit streams. Furthermore, a clock recovery circuit was assembled using the packaged XOR IC, a waveguide filter and a commercial amplifier; it offers the practical system-bit-rate of 39. 81312 GHz with the low rms jitter of 900 fs.

The authors report on a 22-Gbit/s static decision IC fabricated with 0. 12-µm GaAs MESFETs. The key to attaining high-speed decision IC is the employment of a novel high-speed D-type flip-flop (D-FF). The D-FF succeeds in faster operation through the simplification of the circuitry and the reduction of the transition time of the output voltages.

A high-speed static logic circuit, the 1:8 demultiplexer (DEMUX), fabricated using single-gate CMOS technology (single-gate means the structure consisting of n+ poly-Si gate for both NMOS and PMOS transistors) has been demonstrated. To suppress short-channel effects in PMOS transistors, we only used the low-energy ion implantation (I/I) of BF2 at 10 keV for counterdoping of the channel and that at 5 keV for source/drain (S/D) extension. To control the threshold voltage Vth of PMOS transistors precisely, the channel dopants were implanted after the growth of the gate oxide because of the suppression of the transient-enhanced diffusion (TED) of boron, and the suppression of boron out-diffusion. A tree-type 1:8 DEMUX circuit composed of 0. 134 µm gate CMOS transistors operates at a high speed of 3.1 GHz and consumes a low power of 35.5 mW/GHz at VDD = 2.0 V. In this single-gate CMOS circuit, down to this small gate length, the maximum operating frequency of the DEMUX circuit increases proportionally with an increase of the inverse of the gate length without an increase of power consumption per GHz. At a practical 2.48832 Gb/s operation, the power consumption was 88 mW, and the phase margin between the input clock signal and the input data signal was 260 ps. It is suggested that a circuit composed of a single-gate CMOS transistor with 0.15 µm gate generation can be applicable to high speed ICs.

The Scalable-Delay-Insensitive (SDI) model is proposed for high-performance asynchronous system design. In this paper, we focus on checking whether a circuit under SDI model satisfies some untimed properties, and formally show that checking these properties in the SDI model can be reduced to checking the same properties in the bounded delay model. This result suggests that the existing verification algorithms for the bounded delay model can be used for the verification of SDI circuits, which significantly helps the designers of SDI circuits.

In this paper, we present an efficient approach for technology scaling of MOS analog circuits by using circuit optimization techniques. Our new method is based on matching equivalent circuit parameters between a previously designed circuit and the circuit undergoing redesign. This method has been applied to a MOS operational amplifier. We were able to produce a redesigned circuit with almost the same performance in under 4 hours, making this method 5 times more efficient than conventional methods

The system architectures, which allow a high performance fully balanced (FB) system based on ordinary/modified single-ended opamps to be implemented, are investigated and the basic and general requirements are formulated. Two new methods of an FB analog system design, which contribute towards achieving both a high performance IC system implementation and a great reduction of the design time are presented. It is shown that a single-ended system based on any type of opamp (rail-to-rail, constant gm, etc. ), realized in any technology (CMOS, bipolar, BiCMOS, GaAs), can be easily and effectively converted to its FB counterpart in a very practical way. Using the proposed rules, any FB system implementation with opamps (data converter, modulator, filter, etc. ) requires only a single-ended system version design and the drawbacks related to a conventional FB system design are avoided. The principles of the design are pointed out and they are verified by experimental results.

This paper describes a 10 bit CMOS current-mode A/D converter with a current predictor and a modular current reference circuit. A current predictor and a modular current reference circuit are employed to reduce the number of comparator and reference current mirrors and consequently to decrease a power dissipation. The 10 bit current-mode A/D converter is fabricated by the 0.6 µm n-well double poly/triple metal CMOS technology. The measurement results show the input current range of 16 µA to 528 µA, DNL and INL of 0.5 LSB and 1.0 LSB, conversion rate of 10 Msamples, and power dissipation of 94.4 mW with a power supply of 5 V. The effective chip area excluding the pads is 1.8 mm 2.4 mm.

A chaotic noise is one of the most important implements for information processing such as neural networks. It has been suggested that chaotic neural networks have high performance ability for information processing. In this paper, we report two designs of a compact chaotic noise generator for large integration circuits using CMOS technology. The chaotic noise is generated using map chaos. We design both of the logistic map type and the tent map type circuits. These chaotic noise generators are compact as compared with the other circuits. The results show that the successful chaotic operations of the circuits because of the positive Lyapunov number. We calculate the Lyapunov exponents to certify the results of the chaotic operations. However, it is hard to estimate its accurate number for noisy data using the conventional method. And hence, we propose the modified calculation of the Lyapunov exponent for noisy data. These two circuits are expected to be utilized for various applications.

Spot-size-converter integrated semiconductor optical amplifiers have been developed as gate elements for optical switch matrices. An S-shape waveguide has been introduced to prevent re-coupling of unguided light to the output fiber. An angled-facet structure effectively suppressed light reflection at the end facets. Consequently, a high extinction ratio of 70 dB and a high fiber-to-fiber gain of 20 dB were achieved. Sufficient optical coupling characteristics to a flat-ended single-mode fiber with a coupling loss of 3.5 dB were also demonstrated.

Spot-size-converter integrated semiconductor optical amplifiers have been developed as gate elements for optical switch matrices. An S-shape waveguide has been introduced to prevent re-coupling of unguided light to the output fiber. An angled-facet structure effectively suppressed light reflection at the end facets. Consequently, a high extinction ratio of 70 dB and a high fiber-to-fiber gain of 20 dB were achieved. Sufficient optical coupling characteristics to a flat-ended single-mode fiber with a coupling loss of 3.5 dB were also demonstrated.