Verification of Scalable-Delay-Insensitive Asynchronous Circuits
Summary :
The Scalable-Delay-Insensitive (SDI) model is proposed for high-performance asynchronous system design. In this paper, we focus on checking whether a circuit under SDI model satisfies some untimed properties, and formally show that checking these properties in the SDI model can be reduced to checking the same properties in the bounded delay model. This result suggests that the existing verification algorithms for the bounded delay model can be used for the verification of SDI circuits, which significantly helps the designers of SDI circuits.
- Publication
- IEICE TRANSACTIONS on Information Vol.E82-D No.3 pp.701-703
- Publication Date
- 1999/03/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- LETTER
- Category
- Fault Tolerant Computing
Authors
Keyword
Latest Issue
Copyrights notice of machine-translated contents
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Cite this
Copy
Atsushi YAMAZAKI, Hiroshi RYU, Tomohiro YONEDA, "Verification of Scalable-Delay-Insensitive Asynchronous Circuits" in IEICE TRANSACTIONS on Information,
vol. E82-D, no. 3, pp. 701-703, March 1999, doi: .
Abstract: The Scalable-Delay-Insensitive (SDI) model is proposed for high-performance asynchronous system design. In this paper, we focus on checking whether a circuit under SDI model satisfies some untimed properties, and formally show that checking these properties in the SDI model can be reduced to checking the same properties in the bounded delay model. This result suggests that the existing verification algorithms for the bounded delay model can be used for the verification of SDI circuits, which significantly helps the designers of SDI circuits.
URL: https://global.ieice.org/en_transactions/information/10.1587/e82-d_3_701/_p
Copy
@ARTICLE{e82-d_3_701,
author={Atsushi YAMAZAKI, Hiroshi RYU, Tomohiro YONEDA, },
journal={IEICE TRANSACTIONS on Information},
title={Verification of Scalable-Delay-Insensitive Asynchronous Circuits},
year={1999},
volume={E82-D},
number={3},
pages={701-703},
abstract={The Scalable-Delay-Insensitive (SDI) model is proposed for high-performance asynchronous system design. In this paper, we focus on checking whether a circuit under SDI model satisfies some untimed properties, and formally show that checking these properties in the SDI model can be reduced to checking the same properties in the bounded delay model. This result suggests that the existing verification algorithms for the bounded delay model can be used for the verification of SDI circuits, which significantly helps the designers of SDI circuits.},
keywords={},
doi={},
ISSN={},
month={March},}
Copy
TY - JOUR
TI - Verification of Scalable-Delay-Insensitive Asynchronous Circuits
T2 - IEICE TRANSACTIONS on Information
SP - 701
EP - 703
AU - Atsushi YAMAZAKI
AU - Hiroshi RYU
AU - Tomohiro YONEDA
PY - 1999
DO -
JO - IEICE TRANSACTIONS on Information
SN -
VL - E82-D
IS - 3
JA - IEICE TRANSACTIONS on Information
Y1 - March 1999
AB - The Scalable-Delay-Insensitive (SDI) model is proposed for high-performance asynchronous system design. In this paper, we focus on checking whether a circuit under SDI model satisfies some untimed properties, and formally show that checking these properties in the SDI model can be reduced to checking the same properties in the bounded delay model. This result suggests that the existing verification algorithms for the bounded delay model can be used for the verification of SDI circuits, which significantly helps the designers of SDI circuits.
ER -
English
