We investigate the engineering of the impurity bands in photonic crystals (PCs) for realizing high-efficiency wave guiding, all-optical switching and optical delay for ultrashort optical pulses. It is found that quasi-flat impurity bands suitable for the transmission of ultrashort pulses can be achieved by properly controlling the configuration of coupled cavity waveguides (CCWs). At sharp corners, high bending efficiency is obtained over the entire impurity band. All-optical switching can be realized by creating a dynamical band gap at the center of an impurity band. The concentration of electromagnetic wave at defect regions leads to high switching efficiency while the tunable feature of PC defects makes all-optical control possible. It is also revealed that CCWs with quasi-flat impurity bands provide efficient group delay for ultrashort pulses with negligible attenuation and distortion. From the viewpoint of practical fabrication, the effect of disorder on the transmission property of impurity bands is discussed and the criterion for localization transition is determined.

The design aspects of the bulk InGaAsP semiconductor optical amplifier integrated Mach-Zehnder interferometer (SOA-MZI) optimized for 40 Gbps-NRZ all optical wavelength conversion are described. The dimensions of the SOA active waveguide have been optimized for fast gain recovery by maximizing the gain and adjusting the wavelength-converted NRZ waveforms. Submicron-width buried heterostructure (BH) SOA waveguides were fabricated successfully and showed little leakage current. The experimental wavelength-converted optical waveform agreed well to the numerical simulations, and mask-compliant 40 G-NRZ wavelength-converted waveform was obtained by the optimized SOA-MZI. 40 G-NRZ full C-band operation and polarization-insensitive operation of SOA-MZI were also achieved.

A high-speed static logic circuit, the 1:8 demultiplexer (DEMUX), fabricated using single-gate CMOS technology (single-gate means the structure consisting of n+ poly-Si gate for both NMOS and PMOS transistors) has been demonstrated. To suppress short-channel effects in PMOS transistors, we only used the low-energy ion implantation (I/I) of BF2 at 10 keV for counterdoping of the channel and that at 5 keV for source/drain (S/D) extension. To control the threshold voltage Vth of PMOS transistors precisely, the channel dopants were implanted after the growth of the gate oxide because of the suppression of the transient-enhanced diffusion (TED) of boron, and the suppression of boron out-diffusion. A tree-type 1:8 DEMUX circuit composed of 0. 134 µm gate CMOS transistors operates at a high speed of 3.1 GHz and consumes a low power of 35.5 mW/GHz at VDD = 2.0 V. In this single-gate CMOS circuit, down to this small gate length, the maximum operating frequency of the DEMUX circuit increases proportionally with an increase of the inverse of the gate length without an increase of power consumption per GHz. At a practical 2.48832 Gb/s operation, the power consumption was 88 mW, and the phase margin between the input clock signal and the input data signal was 260 ps. It is suggested that a circuit composed of a single-gate CMOS transistor with 0.15 µm gate generation can be applicable to high speed ICs.

SiGe HBTs with doping level inversion, that is, a higher dopant concentration in the base than in the emitter, are realized based on the double-polysilicon self-aligned transistor scheme by means of selective epitaxy performed in a production CVD reactor. The effects of the Ge profile in the base on the transistor performance are explored. The fabricated HBT with a 12-27% graded Ge profile demonstrates a maximum cutoff frequency of 88 GHz, a maximum oscillation frequency of 65 GHz, and an ECL gate delay time of 13.8 ps.

We have succeeded in demonstrating high-performance four-channel 25 Gb/s integrated receiver for 100 Gb/s Ethernet with a built-in spatial Demux optics and an integrated PD array. All components which configure to the Demux optics adhered to a prism. Because of the shaping accuracy for prism, the insertion loss was able to suppress to 0.8 dB with small size. The connection point of the package for high speed electrical signals was improved to decrease the transmission loss. The small size of 12 mm 17 mm 7 mm compact package with a side-wall electrical connector has been achieved, which is compatible with the assembly in CFP2 form-factor. We observed the sensitivity at average power of -12.1 dBm and the power penalty of sensitivity due to the crosstalk of less than 0.1 dB.