The search functionality is under construction.

Author Search Result

[Author] Hiroaki TSUTSUI(2hit)

1-2hit
  • Improved IMD Characteristics in L/S-Band GaAs FET Power Amplifiers by Lowering Drain Bias Circuit Impedance

    Isao TAKENAKA  Hidemasa TAKAHASHI  Kazunori ASANO  Kohji ISHIKURA  Junko MORIKAWA  Hiroaki TSUTSUI  Masaaki KUZUHARA  

     
    PAPER

      Vol:
    E82-C No:5
      Page(s):
    730-736

    This paper describes a high-power and low-distortion AlGaAs/GaAs HFET amplifier developed for digital cellular base station system. We proved experimentally that distortion characteristics such as IMD (Intermodulation Distortion) or NPR (Noise Power Ratio) are drastically degraded when the absolute value of the drain bias circuit impedance at low frequency are high. Based on the experimental results, we have designed the drain bias circuit not to influence the distortion characteristics. The developed amplifier employed two pairs of pre-matched GaAs chips mounted on a single package and the total output-power was combined in push-pull configuration with a microstrip balun circuit. The push-pull amplifier demonstrated state-of-the-art performance of 140 W output-power with 11.5 dB linear gain at 2.2 GHz. In addition, it exhibited extremely low distortion performance of less than 30 dBc at two-tone total output-power of 46 dBm. These results indicate that the design of the drain bias circuit is of great importance to achieve improved IMD characteristics while maintaining high power performance.

  • ECL-Compatible Low-Power-Consumption 10-Gb/s GaAs 8:1 Multiplexer and 1:8 Demultiplexer

    Nobuhide YOSHIDA  Masahiro FUJII  Takao ATSUMO  Keiichi NUMATA  Shuji ASAI  Michihisa KOHNO  Hirokazu OIKAWA  Hiroaki TSUTSUI  Tadashi MAEDA  

     
    PAPER-Low Power-Consumption RF ICs

      Vol:
    E82-C No:11
      Page(s):
    1992-1999

    An emitter coupled logic (ECL) compatible low-power GaAs 8:1 multiplexer (MUX) and 1:8 demultiplexer (DEMUX) for 10-Gb/s optical communication systems has been developed. In order to decrease the power consumption and to maximize the timing margin, we estimated the power consumption for direct-coupled FET logic (DCFL) and source-coupled FET logic (SCFL) circuits in terms of the D-type flip-flop (D-FF) operating speed and the duty-ratio variation. Based on the result, we used SCFL circuits in the clock-generating circuit and the circuits operating at 10 Gb/s, and we used DCFL circuits in the circuits operating below 5 Gb/s. These ICs, which are mounted on ceramic packages, operate at up to 10 Gb/s with power consumption of 1.2 W for the 8:1 MUX and 1.0 W for the 1:8 DEMUX. This is the lowest power consumption yet reported for 10-Gb/s 8:1 MUX and 1:8 DEMUX.