Ultra-low-power-consumption and high-speed DCFL circuits have been fabricated by using 0.2-µm Y-shaped gate E/D-heterojunction-FETs (HJFETs) with a high-aspect-ratio gate-structure, which has an advantage of reducing the gate-fringing capacitance (Cf) to about a half of that of a conventional low-aspect-ratio one. A fabricated 51-stage ring oscillator with the 0.2-µm Y-shaped gate n-AlGaAs/i-InGaAs E/D-HJFETs shows the lowest power-delay product of 0.21 fJ with an unloaded propagation delay of 34.9 ps at a supply voltage (VDD) of 0.4 V. We also analyze the DCFL switching characteristics by taking into account the intrinsic gate-to-source capacitance (Cgsint) and the Cf. The analysis results for the power-delay products agree well with our experimental results. Our analysis also indicates the DCFL circuit with the high-aspect-ratio Y-shaped gate E/D-HJFETs can reduce the power-delay products by 35% or more below 0.25-µm gate-length as compared to conventional ones with the low-aspect-ratio Y-shaped gate HJFETs. These results clarify that the Cf-reduction of the Y-shaped gate HJFETs is more effective in improving the power-delay products than reducing the gate-length.

A high speed and low power consumption SCFL circuit design with low supply voltage is proposed. Focusing on the relationship between logic swing and supply voltage, the lower limit for the supply voltage is presented. Theoretical analysis and circuit simulation indicates that the logic swing needs to be optimized to maintain high average gm within the swing. An SCFL D-FF fabricated using a 0.25 µm n-AlGaAs/i-InGaAs HJFET process operates at up to 10 Gbps with power consumption as low as 19 mW at a supply voltage of 1.3 V.

An emitter coupled logic (ECL) compatible low-power GaAs 8:1 multiplexer (MUX) and 1:8 demultiplexer (DEMUX) for 10-Gb/s optical communication systems has been developed. In order to decrease the power consumption and to maximize the timing margin, we estimated the power consumption for direct-coupled FET logic (DCFL) and source-coupled FET logic (SCFL) circuits in terms of the D-type flip-flop (D-FF) operating speed and the duty-ratio variation. Based on the result, we used SCFL circuits in the clock-generating circuit and the circuits operating at 10 Gb/s, and we used DCFL circuits in the circuits operating below 5 Gb/s. These ICs, which are mounted on ceramic packages, operate at up to 10 Gb/s with power consumption of 1.2 W for the 8:1 MUX and 1.0 W for the 1:8 DEMUX. This is the lowest power consumption yet reported for 10-Gb/s 8:1 MUX and 1:8 DEMUX.