0.21-fJ GaAs DCFL Circuits Using 0.2-µm Y-Shaped Gate AlGaAs/InGaAs E/D-HJFETs

Shigeki WADA; Masatoshi TOKUSHIMA; Masaoki ISHIKAWA; Nobuhide YOSHIDA; Masahiro FUJII; Tadashi MAEDA

0.21-fJ GaAs DCFL Circuits Using 0.2-µm Y-Shaped Gate AlGaAs/InGaAs E/D-HJFETs

Shigeki WADA, Masatoshi TOKUSHIMA, Masaoki ISHIKAWA, Nobuhide YOSHIDA, Masahiro FUJII, Tadashi MAEDA

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Ultra-low-power-consumption and high-speed DCFL circuits have been fabricated by using 0.2-µm Y-shaped gate E/D-heterojunction-FETs (HJFETs) with a high-aspect-ratio gate-structure, which has an advantage of reducing the gate-fringing capacitance (C_f) to about a half of that of a conventional low-aspect-ratio one. A fabricated 51-stage ring oscillator with the 0.2-µm Y-shaped gate n-AlGaAs/i-InGaAs E/D-HJFETs shows the lowest power-delay product of 0.21 fJ with an unloaded propagation delay of 34.9 ps at a supply voltage (V_DD) of 0.4 V. We also analyze the DCFL switching characteristics by taking into account the intrinsic gate-to-source capacitance (C_gs^int) and the C_f. The analysis results for the power-delay products agree well with our experimental results. Our analysis also indicates the DCFL circuit with the high-aspect-ratio Y-shaped gate E/D-HJFETs can reduce the power-delay products by 35% or more below 0.25-µm gate-length as compared to conventional ones with the low-aspect-ratio Y-shaped gate HJFETs. These results clarify that the C_f-reduction of the Y-shaped gate HJFETs is more effective in improving the power-delay products than reducing the gate-length.

Publication: IEICE TRANSACTIONS on Electronics Vol.E82-C No.3 pp.491-497

Publication Date: 1999/03/25

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Type of Manuscript: Special Section PAPER (Special Issue on Ultra-High-Speed IC and LSI Technology)

Category: Compound Semiconductor Devices

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Shigeki WADA, Masatoshi TOKUSHIMA, Masaoki ISHIKAWA, Nobuhide YOSHIDA, Masahiro FUJII, Tadashi MAEDA, "0.21-fJ GaAs DCFL Circuits Using 0.2-µm Y-Shaped Gate AlGaAs/InGaAs E/D-HJFETs" in IEICE TRANSACTIONS on Electronics, vol. E82-C, no. 3, pp. 491-497, March 1999, doi: .
Abstract: Ultra-low-power-consumption and high-speed DCFL circuits have been fabricated by using 0.2-µm Y-shaped gate E/D-heterojunction-FETs (HJFETs) with a high-aspect-ratio gate-structure, which has an advantage of reducing the gate-fringing capacitance (C_f) to about a half of that of a conventional low-aspect-ratio one. A fabricated 51-stage ring oscillator with the 0.2-µm Y-shaped gate n-AlGaAs/i-InGaAs E/D-HJFETs shows the lowest power-delay product of 0.21 fJ with an unloaded propagation delay of 34.9 ps at a supply voltage (V_DD) of 0.4 V. We also analyze the DCFL switching characteristics by taking into account the intrinsic gate-to-source capacitance (C_gs^int) and the C_f. The analysis results for the power-delay products agree well with our experimental results. Our analysis also indicates the DCFL circuit with the high-aspect-ratio Y-shaped gate E/D-HJFETs can reduce the power-delay products by 35% or more below 0.25-µm gate-length as compared to conventional ones with the low-aspect-ratio Y-shaped gate HJFETs. These results clarify that the C_f-reduction of the Y-shaped gate HJFETs is more effective in improving the power-delay products than reducing the gate-length.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e82-c_3_491/_p

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@ARTICLE{e82-c_3_491,
author={Shigeki WADA, Masatoshi TOKUSHIMA, Masaoki ISHIKAWA, Nobuhide YOSHIDA, Masahiro FUJII, Tadashi MAEDA, },
journal={IEICE TRANSACTIONS on Electronics},
title={0.21-fJ GaAs DCFL Circuits Using 0.2-µm Y-Shaped Gate AlGaAs/InGaAs E/D-HJFETs},
year={1999},
volume={E82-C},
number={3},
pages={491-497},
abstract={Ultra-low-power-consumption and high-speed DCFL circuits have been fabricated by using 0.2-µm Y-shaped gate E/D-heterojunction-FETs (HJFETs) with a high-aspect-ratio gate-structure, which has an advantage of reducing the gate-fringing capacitance (C_f) to about a half of that of a conventional low-aspect-ratio one. A fabricated 51-stage ring oscillator with the 0.2-µm Y-shaped gate n-AlGaAs/i-InGaAs E/D-HJFETs shows the lowest power-delay product of 0.21 fJ with an unloaded propagation delay of 34.9 ps at a supply voltage (V_DD) of 0.4 V. We also analyze the DCFL switching characteristics by taking into account the intrinsic gate-to-source capacitance (C_gs^int) and the C_f. The analysis results for the power-delay products agree well with our experimental results. Our analysis also indicates the DCFL circuit with the high-aspect-ratio Y-shaped gate E/D-HJFETs can reduce the power-delay products by 35% or more below 0.25-µm gate-length as compared to conventional ones with the low-aspect-ratio Y-shaped gate HJFETs. These results clarify that the C_f-reduction of the Y-shaped gate HJFETs is more effective in improving the power-delay products than reducing the gate-length.},
keywords={},
doi={},
ISSN={},
month={March},}

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TY - JOUR
TI - 0.21-fJ GaAs DCFL Circuits Using 0.2-µm Y-Shaped Gate AlGaAs/InGaAs E/D-HJFETs
T2 - IEICE TRANSACTIONS on Electronics
SP - 491
EP - 497
AU - Shigeki WADA
AU - Masatoshi TOKUSHIMA
AU - Masaoki ISHIKAWA
AU - Nobuhide YOSHIDA
AU - Masahiro FUJII
AU - Tadashi MAEDA
PY - 1999
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E82-C
IS - 3
JA - IEICE TRANSACTIONS on Electronics
Y1 - March 1999
AB - Ultra-low-power-consumption and high-speed DCFL circuits have been fabricated by using 0.2-µm Y-shaped gate E/D-heterojunction-FETs (HJFETs) with a high-aspect-ratio gate-structure, which has an advantage of reducing the gate-fringing capacitance (C_f) to about a half of that of a conventional low-aspect-ratio one. A fabricated 51-stage ring oscillator with the 0.2-µm Y-shaped gate n-AlGaAs/i-InGaAs E/D-HJFETs shows the lowest power-delay product of 0.21 fJ with an unloaded propagation delay of 34.9 ps at a supply voltage (V_DD) of 0.4 V. We also analyze the DCFL switching characteristics by taking into account the intrinsic gate-to-source capacitance (C_gs^int) and the C_f. The analysis results for the power-delay products agree well with our experimental results. Our analysis also indicates the DCFL circuit with the high-aspect-ratio Y-shaped gate E/D-HJFETs can reduce the power-delay products by 35% or more below 0.25-µm gate-length as compared to conventional ones with the low-aspect-ratio Y-shaped gate HJFETs. These results clarify that the C_f-reduction of the Y-shaped gate HJFETs is more effective in improving the power-delay products than reducing the gate-length.
ER -