This report presents Dual Field-modulating-Plates (Dual-FP) technology for a 28 V operated high power GaAs heterojunction FET (HJFET) amplifier. A developed HJFET has two FP electrodes; the 1st-FP is connected to the gate and the 2nd-FP to the ground. The 2nd-FP suppresses the drain current dispersion effectively cooperating with the 1st-FP, and it can also reduce the gate-drain parasitic capacitance. The developed push-pull amplifier, with four Dual-FPFET chips, demonstrated 55.1 dBm (320 W) output power with a 14.0 dB linear gain and a drain efficiency of 62% at 2.14 GHz. Under two-carrier W-CDMA signals, it showed a high drain efficiency of 30% and low third-order Inter-modulation distortion of -37 dBc at output power of 47.5 dBm.

High-frequency characterization and delay-time analysis have been performed for a short channel AlGaN/GaN heterojunction FET. The fabricated device with a short gate length (Lg) of 0.07 µm exhibited an extrinsic current gain cutoff frequency of 81 GHz and a maximum frequency of oscillation of 190 GHz with a maximum stable gain (MSG) of 8.2 dB at 60 GHz. A new scheme for the delay-time analysis was proposed, in which the effects of rather large series resistance RS + RD are properly taken into account. By applying the new scheme to a device with Lg=0.25 µm, we obtained an effective high-field electron velocity of 1.75107 cm/s, which is consistent with our previous results calculated using Monte Carlo simulation.

This paper describes 1.0 V operation power performance of a double doped AlGaAs/InGaAs/AlGaAs heterojunction FET for personal digital cellular phones. The developed FET with a multilayer cap consisting of a highly Si-doped GaAs, an undoped GaAs and a highly Si-doped AlGaAs exhibited an on-resistance of 1.3 Ωmm and a maximum drain current of 620 mA/mm. A 28 mm gate-width device, operating with a drain bias voltage of 1.0 V, demonstrated an output power of 1.0 W, a power-added efficiency of 59% and an associated gain of 13.7 dB at an adjacent channel leakage power at 50 kHz off-center frequency of -48 dBc with a 950 MHz π/4-shifted quadrature phase shift keying signal.

This paper describes amplification with improved linearity by employing a linearizing circuit in an input circuit of an internally-matched Ku-band high power amplifier. The linearizing circuit is composed of series L, C, R and an FET with grounded source and drain, and is connected between the input signal line and ground. This linearizing circuit was applied to a Ku-band 10 W output power amplifier utilizing a 25.2 mm gate-width double-doped Heterojunction FET. The power amplifier demonstrated a 8 dB reduction of the third-order intermodulation at about 6 dB output power backoff point from the 2 dB output compression point.

Ultra-low-power-consumption and high-speed DCFL circuits have been fabricated by using 0.2-µm Y-shaped gate E/D-heterojunction-FETs (HJFETs) with a high-aspect-ratio gate-structure, which has an advantage of reducing the gate-fringing capacitance (Cf) to about a half of that of a conventional low-aspect-ratio one. A fabricated 51-stage ring oscillator with the 0.2-µm Y-shaped gate n-AlGaAs/i-InGaAs E/D-HJFETs shows the lowest power-delay product of 0.21 fJ with an unloaded propagation delay of 34.9 ps at a supply voltage (VDD) of 0.4 V. We also analyze the DCFL switching characteristics by taking into account the intrinsic gate-to-source capacitance (Cgsint) and the Cf. The analysis results for the power-delay products agree well with our experimental results. Our analysis also indicates the DCFL circuit with the high-aspect-ratio Y-shaped gate E/D-HJFETs can reduce the power-delay products by 35% or more below 0.25-µm gate-length as compared to conventional ones with the low-aspect-ratio Y-shaped gate HJFETs. These results clarify that the Cf-reduction of the Y-shaped gate HJFETs is more effective in improving the power-delay products than reducing the gate-length.

This paper describes design approach and power performance of a single 1. 5 V operation two-stage power amplifier MMIC for 2. 4 GHz wireless local area network applications. The MMIC with 0. 760. 96 mm2 area includes SrTiO3 (STO) capacitors with a high capacitance density of 8. 0 fF/µm2 and double-doped AlGaAs/InGaAs/AlGaAs heterojunction FETs with a shallow threshold voltage of -0. 24 V. Utilizing a series STO capacitor and a shunt inductor as an output matching circuit, the total chip size was reduced by 40% as compared with an MMIC utilizing SiNx capacitors. Under single 1.5 V operation, the developed MMIC delivered an output power of 110 mW (20.4 dBm) and a power-added efficiency (PAE) of 36.7% with an associated gain of 20.0 dB at 2.4 GHz. Even operated at a drain bias voltage of 0.8 V, the MMIC exhibited a high PAE of 31.0%.

A buried gate AlGaAs/InGaAs heterojunction FET (HJFET) with gate breakdown voltage of 30 V was examined for high drain bias (higher than 10 V) operation. High breakdown voltage was realized due to the optimization of the narrow recess depth. A 1.4 mm HJFET has exhibited an output power of 30.2 dBm (1050 mW) with 50% power added efficiency (PAE) and 12.1 dB linear gain at 12 GHz with a 13 V drain bias. An internal matching circuit for a 16.8 mm HJFET was designed using a large-signal load impedance determined from load-pull measurement. The 16.8 mm internally-matched HJFET has delivered 38.9 dBm (7.8 W) output power with 46% PAE and 11.6 dB linear gain at 12 GHz with a drain bias of 13 V. This is the first report of higher than 10 V operation of an X- and Ku-band power HJFET with the excellent power performance.

A high speed and low power consumption SCFL circuit design with low supply voltage is proposed. Focusing on the relationship between logic swing and supply voltage, the lower limit for the supply voltage is presented. Theoretical analysis and circuit simulation indicates that the logic swing needs to be optimized to maintain high average gm within the swing. An SCFL D-FF fabricated using a 0.25 µm n-AlGaAs/i-InGaAs HJFET process operates at up to 10 Gbps with power consumption as low as 19 mW at a supply voltage of 1.3 V.

This paper describes 950 GHz power performance of double-doped AlGaAs/InGaAs/AlGaAs heterojunction field-effect transistors (HJFET) operated at a drain bias voltage ranging from 2.5 to 3.5 V. The developed 1.0 µm gatelength HJFET exhibited a maximum drain current (Imax) of 500 mA/mm, a transconductance (gm) of 300 mS/mm, and a gate-to-drain breakdown voltage of 11 V. Operated at 3.0 V, a 17.5 mm gate periphery HJFET showed 1.4 W Pout and -50.3 dBc adjacent channel leakage power at a 50 kHz off-carrier frequency from 950 MHz with 50% PAE. Harmonic balance simulations revealed that the flat gm characteristics of the HJFET with respect to gate bias voltage are effective to suppress intermodulation distortion under large signal operation. The developed HJFET has great potential for small-sized digital cellular power applications operated at a low DC supply voltage.

We discuss delay times derived from the current gain cutoff frequency of a heterostructure field effect transistor and describe three types of novel channel structures for millimeter-wave InP-based HFETs. The first structure discussed is a lattice-matched InGaAs HEMT with high state-of-the art performance. The second structure is an InAs-inserted InGaAs HEMT which harnesses the superior transport properties of InAs. Fabricated devices show high electron mobility of 12,800 cm2/Vs and high transconductance over 1.4 S/mm for a 0.6-µm-gate length. The effective saturation velocity in the device derived from the current gain cutoff frequency in 3.0107 cm/s. The third one is an InGaAs/InP double-channel HFET that utilizes the superior transport properties of InP at a high electric field. Fabricated double-channel devices show kink-free characteristics, high carrier density of 4.51012 cm-2 and high transconductance of 1.3 S/mm for a 0.6-µm-gate length. The estimated effective saturation velocity in these devices is 4.2107 cm/s. Also included is a discussion of the current gain cutoff frequency of ultra-short channel devices.