Application of microwave and millimeter-wave circuit technologies to InGaP-HBT ICs for 40-Gbps optical-transmission systems is demonstrated from two aspects. First, ICs for various important functions -- amplification of data signals, amplification, frequency doubling, and phase control of clock signals -- are successfully developed based on microwave and millimeter-wave circuit configurations mainly composed of distributed elements. A distributed amplifier exhibits ≥164-GHz gain-bandwidth product with low power consumption (PC) of 71.2 mW. A 20/40-GHz-band frequency doubler achieves wideband performance (40%) with low PC (26 mW) by integrating a high-pass filter and a buffer amplifier (as a low-pass filter). A compact 40-GHz analog phase shifter, 20- and 40-GHz-band clock amplifiers with low PC are also realized. Second, a familiar concept in microwave-circuit design is applied to a high-speed digital circuit. A new approach -- inserting impedance-transformer circuits -- to enable 'impedance matching' in digital ICs is successfully applied to a 40-Gbps decision circuit to prevent unwanted gain peaking and jitter increase caused by transmission lines without sacrificing chip size.

Recessed-gate DMTs (doped-channel hetero-MISFETs) with i-AlGaAs/n-GaAs structure and pseudomorphic i-AlGaAs/n-InGaAs/i-GaAs structure have been developed. Broad plateaus in gm and fT provide evidence that the DMTs make the devices suitable for high-speed large-signal operation. GaAs DMTs with 0.35 µm-length have gate turn on voltage of 0.7 V, maximum transconductance of 320 mS/mm and fT of 41 GHz. Pseudomorphic DMTs have gate turn on voltage of 0.9 V, maximum transconductance of 320 mS/mm, fT of 42 GHz and have the enhanced advantages of high current drivability and large gate swing. Further more, with the use of the recessed-gate DMTs, a high-speed laser driver IC for multi-Gb/s optical communication systems are demonstrated. This laser driver IC operates at 10 Gb/s with rise and fall times as fast as 40 psec, and it can drive up to 60 mA into a 25 Ω load.

We derived explicit formulas for evaluating the error vector magnitude (EVM) from the amplitude distortion (AM-AM) and phase distortion (AM-PM) of power amplifiers (PAs) in orthogonal frequency-division multiplexing (OFDM) systems, such as the IEEE 802.11a/g wireless local area networks (WLANs) standards. We demonstrated that the developed formulas allowed EVM simulation of a memoryless PA using only a single-tone response (i.e. without OFDM modulation and demodulation), thus enabling us to easily simulate the EVM using a harmonic-balance (HB) simulator. This HB simulation technique reduced the processing time required to simulate the EVM of a PA for the IEEE 802.11a standard by a factor of ten compared to a system-level (SL) simulation. We also demonstrated that the measured EVM of a PA module for the IEEE 802.11g could accurately be predicted by applying the measured static AM-AM and AM-PM characteristics to the derived formulas.

A high speed and low power consumption SCFL circuit design with low supply voltage is proposed. Focusing on the relationship between logic swing and supply voltage, the lower limit for the supply voltage is presented. Theoretical analysis and circuit simulation indicates that the logic swing needs to be optimized to maintain high average gm within the swing. An SCFL D-FF fabricated using a 0.25 µm n-AlGaAs/i-InGaAs HJFET process operates at up to 10 Gbps with power consumption as low as 19 mW at a supply voltage of 1.3 V.