A device simulator that simulates device performance in the cyclic bias steady state was developed, and it was applied to GaAs hetero-junction FET (HJFET) pulse pattern effect. Although there is a large time-constant difference between the pulse signals and deep trap reactions, the simulator searches the cyclic bias steady states at about 30 iterations. A non-linear shift in the drain current level with the mark ratio was confirmed, which has been estimated from the rate equation of electron capture and emission based on Shockley-Read-Hall statistics for deep traps.

A model for the enhancement-mode operation of an AlGaN/GaN metal-insulator-semiconductor heterostructure field-effect transistor (MIS-HFET) under DC and AC conditions is proposed. In DC operation at positive gate voltages, the MIS-HFET can be divided into a transistor area and a resistor area due to the diode nature of the insulator/AlGaN interface. The transistor area shrinks with the increases in gate voltage. The intrinsic-transistor gate-length reduction causes a drain current increase. The I-V characteristics based on the gradual channel approximation are derived. The ID hysteresis of the MIS-HFET is investigated by a circuit simulation using SPICE. We have confirmed that the hysteresis was caused by the phase difference between the potential variation of the gate insulator/AlGaN interface and that of the gate electrode due to CR components in the gate structure.

Low-power dry-etching process has been adopted to study the influence of dry-etching on Ohmic contact to p-GaN. When the surface layer of as-grown p-GaN was removed by low-power SiCl4/Cl2-etching, no Ohmic contact can be formed on the low-power dry-etched p-GaN. The same dry-etching process was also applied on n-GaN to understand the influence of the low-power dry-etching process. By capacitance-voltage (C-V) measurement, the Schottky barrier heights (SBHs) of p-GaN and n-GaN were measured. By comparing the change of measured SBHs on p-GaN and n-GaN, it was suggested that etching damage is not the only reason responsible for the degraded Ohmic contacts to dry-etched p-GaN and for Ohmic contact formatin, the original surface layer of as-grown p-GaN have some special properties, which were removed by dry-etching process. To partially recover the original surface of as-grown p-GaN, high temperature annealing (1000C 30 s) was tried on the SiCl4/Cl2-etched p-GaN and Ohmic contact was obtained.

We analyzed passivation film and the AlGaN surface states using open-gated structures of AlGaN/GaN HFETs by numerical simulation and experiments. From the analyses, we confirmed that insulating film conductivity plays the prominent roles in device performances of the wide bandgap semiconductor device. Device simulation confirmed that the difference in ID-VG characteristics is due to the trapping type of the surface states; electron-trap type or hole-trap type. For electron-trap type surface states, the surface potential pinned at electron quasi-Fermi level, which is the same as the channel potential in the open-gated FETs. As a result, surface potential of ungated region is equal to the channel electric potential resulting in the uncontrollability of the channel current by the edge placed gate electrode. For hole-trap type surface states, the surface potential is pinned at hole quasi-Fermi level, which must be the same as the edge placed gate electrode potential. Then, the AlGaN surface potential varies with the electrode potential variation allowing the control of channel current as if the whole channel is covered with a metal electrode. Experiments for open-gated FET with unpassivated surface show no current variation. This corresponds to electron-trap type surface states from the simulation. On the other hand, SiOX evaporated open-gated FET show current control by the gate electrode. The ID-VG characteristics resembles in simulated ID-VG characteristics with hole-trap surface states. However, the estimated time constants for the trap reactions are incredibly long due to the deep energy level for the surface states in wide bandgap semiconductors. In addition, the open-gated FET showed reverse threshold shift to the value expected from the hole-trap pinning levels. So, we concluded that the no current variation for the unpassivated open-gated FET can be attributed to electron traps in the surface states, but the control of the drain current for SiOX deposited open-gated FET is not by surface hole-traps, but by slightly conductive passivation film of SiOX.

DC and RF performances of AlGaN/GaN HEMTs are simulated using a two-dimensional device simulator with the material parameters of GaN and AlGaN. The cut-off frequency is estimated as 205 GHz at the gate length of 0.05 µm and the drain breakdown voltage at this gate length is over 10 V. The values are satisfactory for millimeter wavelength power applications. The use of thin AlGaN layers has key importance to alleviate gate parasitic capacitance effects at this gate length.

Drain collapse in AlGaN/GaN HFET is analyzed using a two-dimensional device simulator. Two-step saturation is obtained, assuming hole-trap type surface states on the AlGaN surface and a short negative-charge-injected region at the drain side of the gate. Due to the surface electric potential pinning by the surface traps, the negative charge injected region forms a constant potential like in a metal gate region and it acts as an FET with a virtual gate. The electron concentration profile reveals that the first saturation occurs by pinch-off in the virtual gate region and the second saturation occurs by the pinch-off in the metal gate region. Due to the short-channel effect of the virtual gate FET, the saturation current increases until it finally reaches the saturation current of the intrinsic metal gate FET. Current collapses with current degradation at the knee voltage in the I-V characteristics can be explained by the formation of the virtual gate.

A high speed and low power consumption SCFL circuit design with low supply voltage is proposed. Focusing on the relationship between logic swing and supply voltage, the lower limit for the supply voltage is presented. Theoretical analysis and circuit simulation indicates that the logic swing needs to be optimized to maintain high average gm within the swing. An SCFL D-FF fabricated using a 0.25 µm n-AlGaAs/i-InGaAs HJFET process operates at up to 10 Gbps with power consumption as low as 19 mW at a supply voltage of 1.3 V.

High-temperature stability of copper (Cu) gate AlGaN/GaN high electron mobility transistors (HEMTs) was investigated. Samples were annealed at various temperatures to monitor the changes on device performances. Current-voltage performance such as drain-source current, transconductance, threshold voltage and gate leakage current has no obvious degradation up to annealing temperature of 500 and time of 5 minutes. Also up to this temperature, no copper diffusion was found at the Cu and AlGaN interface by secondary ion mass spectrometry determination. At annealing temperature of 700 and time of 5 minutes, device performance was found to have degraded. Gate voltage swing increased and threshold voltage shifted due to Cu diffusion into AlGaN. These results indicate that the Schottky contact and device performance of Cu-gate AlGaN/GaN HEMT is stable up to annealing temperature of 500. Cu is a promising candidate as gate metallization for high-performance power AlGaN/GaN HEMTs.

The mechanism of current collapse of AlGaN/GaN heterojunction field-effect transistors (HFETs) was investigated by gate bias stress with and without illumination. It is clarified that there are two positions where negative charges accumulate, at the gate edge and in the bulk epi-layer. In the gate-edge mode, the charge comes either through the passivation film or the AlGaN layer, depending on the resistance of the films. Reduction of leakage current in the passivation film will be important to suppress the surface-related collapse.

To improve the high voltage performance of AlGaN/GaN heterojunction field effect transistors (HFETs), we have fabricated AlGaN/GaN HFETs with p-GaN epi-layer on sapphire substrate with an ohmic contact to the p-GaN (p-sub HFET). Substrate bias dependent threshold voltage variation (VT-VSUB) was used to directly determine the doping concentration profile in the buffer layer. This VT-VSUB method was developed from Si MOSFET. For HFETs, the insulator is formed by epitaxially grown and heterogeneous semiconductor layer while for Si MOSFETs the insulator is amorphous SiO2. Except that HFETs have higher channel mobility due to the epitaxial insulator/semiconductor interface, HFETs and Si MOSFETs are basically the same in the respect of device physics. Based on these considerations, the feasibility of this VT-VSUB method for AlGaN/GaN HFETs was discussed. In the end, the buffer layer doping concentration was measured to be 21017 cm-3, p-type, which is well consistent with the Mg concentration obtained from secondary ion mass spectroscopy (SIMS) measurement.

This investigation of the temperature and illumination effects on the AlGaN/GaN HFET threshold voltage shows that it shifts about -1 V under incandescent lamp or blue LED illumination, while almost no shift takes place under red LED illumination. The temperature coefficient for the threshold voltage shift is +3.44 mV/deg under the illuminations and +0.28 mV/deg in darkness. The threshold voltage variation can be attributed to a virtual back-gate effect caused by light-generated buffer layer potential variations. The expressions for the potential variation are derived using Shockley-Read-Hall (SRH) statistics and the Maxwell-Boltzmann distribution for the carriers and deep traps in the buffer layer. The expressions indicate that large photoresponses will occur when the electron concentration in the buffer layer is extremely small, that is, highly resistive. In semi-insulating substrates, the substrate potential varies so as to keep the trap occupation function constant. The sign and the magnitude of the threshold voltage variation are explained by the shift of the pinning energy calculated from the Fermi-Dirac distribution function.