The relationship between the change in transistor operation regions and the fault behavior of a mixed-signal circuit having a bridging fault was investigated. We also discussed determination of transistors to be observed for estimating the fault behavior. These results will be useful for modeling faulty behaviors and analyzing and diagnosing faults in mixed-signal circuits.

This paper explains a mechanism of common-mode generation on a printed circuit board with a narrow ground pattern. A transmission line has its value of degree of unbalance. At a connection point of two transmission lines having different degrees of unbalance, common mode voltage is generated proportional to the difference, and it drives common mode current. The authors propose a method to evaluate common mode current distribution and verify it by measurement. Although calculated common mode current is larger than measured one by a few dBs, both of them are proportional to the degree of unbalance. An EMI reduction technique, 'unbalance matching,' is also proposed.

In this paper, the evaluation of emission from a PCB by using crosstalk between a low frequency signal trace and a digital signal trace is investigated. These signal traces are closely routed in parallel to each other on the different several signal planes in the PCB. It is shown experimentally that the coupled signal trace with a cable section causes drastic increase of emission from the PCB. From the measurement results of current distribution on the cable section, it is shown that this current distribution contributes to the increase of emission from the PCB. Therefore, emission increasing by coupling between signal traces is evaluated by crosstalk between them. The measurement results of radiation and the calculation results of crosstalk on the PCB (deviation from results of the PCB which is referred, respectively) agree with each other within 2 dB range or 3.5 dB range. This result shows that reduction effect of emission from the PCB can be predicted by calculation results of crosstalk. Moreover, it is shown that evaluation of emission level by using crosstalk is useful to decide PCB's structure for reduction of emission from a high-density assembled PCB. From the viewpoint of practical application, it is effective for the reduction of emission from a PCB to separate a low frequency signal trace from a high-speed digital signal trace by ground plane of a PCB.

This paper describes the mechanisms of power-distribution-plane resonance in multilayer printed circuit boards and the techniques to control the resonance. The power-distribution-plane resonance is responsible for high-level emissions and circuit malfunctions. Controlling the resonance is an effective technique, so adequate characterization of the resonance is necessary to achieve control. The resonance characteristics of four-layer printed circuit boards are investigated experimentally and theoretically by treating the power-distribution planes as a parallel-plate transmission line with decoupling circuits. Analysis of the forward traveling wave shows that the resonance frequency is determined by the phase delay due to wave propagation and by the phase progress of interconnect inductance in the decoupling circuit. Techniques to control the resonance characteristics are investigated. The resonance can be shifted to a higher frequency by adding several decoupling circuits adjacent to the existing decoupling capacitor or by increasing the number of via holes connecting the capacitor mounting pads to the power-distribution planes.

This paper describes the effect of lowering the supply voltage and threshold voltages on the energy reduction of an ultralow-voltage multi-threshold CMOS/SIMOX (MTCMOS/SIMOX) circuit. The energy dissipation is evaluated using a graph with equispeed and equienergy lines on a supply voltage and a threshold voltage plane. In order to draw equispeed and equienergy lines for ultralow-voltage circuits, we propose a modified energy-evaluation model taking into account a input-waveform transition-time of the circuits. The validity of the proposed energy-evaluation model is confirmed by the evaluation of a gate-chain TEG and a 16-bit CLA adder fabricated with 0.25-µm MTCMOS/SIMOX technology. Using the modified model, the energy-reduction effect in lowering the supply voltage is evaluated for a single-Vth fully-depleted CMOS/SOI circuit, a dual-Vth CMOS circuit consisting of fully-depleted low- and medium-Vth MOSFETs, and a triple-Vth MTCMOS/SIMOX circuit. The evaluation reveals that lowering the supply voltage of the MTCMOS/SIMOX circuit to 0.5 V is advantageous for the energy reduction at a constant operating speed.

A lower impedance terminal is necessary for an input terminal of current-mode circuits and an output terminal of voltage-mode circuits to reduce an error and distortion in analog signal processing. Thus, the CMOS circuit with a very low impedance terminal (VLIT circuit) is a useful analog building block to achieve the above purpose. The very low impedance terminal in the VLIT circuit is performed by a shunt-series feedback configuration. However, the feedback generates a problem of instability and/or oscillation at the same time. The problem can be removed by a phase compensation capacitor as known well, but the capacitor is not desirable for integrated circuits due to its large area. This paper proposes a new phase compensation technique for the VLIT circuit. The proposed technique does not need any capacitors to obtain a sufficient phase margin, and instead gives us the appropriate transistor sizes (Width and length of the gate). As a result, the VLIT circuit has an enough phase margin and operates stably.

This paper summarizes power reduction methods applicable for VLSI bus systems in terms of reduction of signal swing, effective capacitance reduction and reduction of signal transition, which have been studied in authors' research group. In each method the basic concept is reviewed quickly along with some examples of its application. A future perspective is also described in conclusion.

A 24-bit, 96 kHz stereo A/D converter (ADC) for DVD-audio has been developed. The single-chip integrates stereo delta-sigma modulators (Δ ΣM's), a voltage reference, and a decimation filter. A fourth-order cascaded Δ ΣM using a local feedback technique was employed to avoid overload without sacrificing noise performance. Low power switched-capacitor techniques were used for implementation. A two-stage decimation filter architecture that reduces digital switching noise was also developed. A merged multi-stage comb filter was used for the first stage, and a bit-serial finite-impulse-response (FIR) filter was used for the second stage. The 18.0 mm2 chip was fabricated in 0.6-µm CMOS with low threshold devices. Measured results show 117 dB A-weighted dynamic range in the 20 kHz passband, with 470 mW power dissipation at 5 V operation.

A tail current source is often employed for many analog building blocks. It can limit the increase of excess power. It can also improve CMRR and PSRR. In this paper, we propose a very high output impedance tail current source for low voltage applications. The proposed tail current source has almost the same output impedance as the conventional cascode type tail current source in theory. Simulation results show that the output impedance of the proposed circuit becomes 1.28 GW at low frequencies. Applying the proposed circuit to a differential amplifier, the CMRR is enhanced by 66.7 dB, compared to the conventional differential amplifier. Moreover, the proposed circuit has the other excellent merit. The output stage of the proposed tail current source can operate at VDS(sat) and a quarter of VDS(sat) of the simple current source in theory and simulation, respectively. For example, in the simulation, when the reference current IREF is set to 100µA, the minimum voltage of the simple current source approximates 0.4 V, whereas that of the proposed current source approximates 0.1 V. Thus, the dynamic range can be enlarged by 0.3 V in this case. The value is still enough large value for low voltage applications. Hence, the proposed tail current source is suitable for low voltage applications.

This paper proposes a realization of power factor function generator having an arbitrary base and power factor which are determined by the ratios of the currents provided from outside of the circuit. The circuit characteristics do not depend on any transistor parameters, temperature, and other environmental conditions. The circuit operation is based on current mode that has a capability of low power supply voltage operation below than 2.0 V. SPICE simulation has been carried out using 0.7 µm BiCMOS parameters and shows quite good transfer characteristics.

High-speed low-power matched filter plays an important role in the fast despreading of spread-signals in wideband code division multiple access (W-CDMA) mobile communications. In this paper, we describe the algorithm and the VLSI-architecture of a complex matched filter chip implemented by our proposed digital-controlled analog parallel operational circuits. The complex matched filter VLSI with variable taps from 4 to 128 is developed for despreading QPSK-modulated spread-signals for W-CDMA communications, which is fabricated by a 2-metal 0.8 µm CMOS technology. The dissipation power of the chip is 225 mW and 130 mW when it operates at the chip-rate of 20 MHz with the supply voltages of 3.0 V and 2.5 V, respectively, and it can be furthermore reduced to 62 mW at chip rate of 10 MHz when the supply voltage is lowered to 2.2 V. The 3-dB cut-off frequency of the fabricated chip is higher than 20 MHz for both 3.0 V and 2.5 V supplies. Comparing to pure digital matched filters, the massive and high-speed despreading operations of the spread-signals are directly carried out in analog domain. As a result, two high-speed analog-to-digital (A/D) converters operating at chip rate are omitted, the inner signal paths and the total dissipation power are greatly reduced.

We have developed a parameter optimization tool, Monte Carlo Josephson simulator (MJSIM), for rapid single flux quantum (RSFQ) digital circuits based on a Monte Carlo yield analysis. MJSIM can generate a number of net lists for the JSIM, where all parameter values are varied randomly according to the Gaussian distribution function, and calculate the circuit yields automatically. MJSIM can also produce an improved parameter set using the algorithm of the center-of-gravity method. In this algorithm, an improved parameter vector is derived by calculating the average of parameter vectors inside and outside the operating region. As a case study, we have optimized the circuit parameters of an RS flip-flop, and investigated the validity and efficiency of this optimization method by considering the convergency and initial condition dependence of the final results. We also proposed a method for accelerating the optimization speed by increasing 3σ spreads of the parameter distribution during the optimization.

Accurate current analysis is required in circuit designs to analyze electromigration failure rate, power consumption, voltage drop, and so on. A charge-based current model for CMOS gates is presented in this paper. The current waveform of a CMOS gate during a transition consists of three components: one occurs when the input changes and the others exist only when the output changes. These three components are characterized by triangular pulses with four parameters which can be easily obtained after timing simulation. This model has been embedded into our switch-level timing simulator to generate the current waveform. The simulated current waveform helps solve the VLSI reliability problems due to electromigration and excess voltage drops in the power buses. When comparing the results obtained by using SPICE with those by our model, we find agreement, especially on the time points at which current pulses occur.

We report on the fabrication and operation of all-NbN single flux quantum (SFQ) circuits with resistively shunted NbN/AlN/NbN tunnel junctions fabricated on silicon substrates. The critical current varied by about 5% in 400 NbN/AlN/NbN junction arrays, where the junction area was 88 µm2. Critical current densities of the NbN/AlN/NbN tunnel junctions showed exponential dependence on the deposition time of the AlN barrier. By using the 12-nm-thick Cu film as shunted resistors, non-hysteretic current-voltage characteristics were achieved. From dc-SQUID measurements, the sheet inductance of our NbN stripline was estimated to be around 1.2 pH at 4.2 K. We designed and fabricated circuits consisting of dc/SFQ converters, Josephson transmission lines, and T flip-flop-based SFQ/dc converters. The circuits demonstrated correct operation with a bias margin of more than 15% at 4.2 K.

Recent progress of high-temperature superconductor Josephson junction technology is reviewed in the light of the future application to digital circuits. Among various types of Josephson junctions so far developed, ramp-edge-type junctions with a barrier layer composed of oxide materials in the vicinity of metal-insulator transition seem to offer a unique opportunity to fulfill all the requirements for digital circuit applications by virtue of their small junction dimensions, overdamped properties and relatively high IcRn product values at the temperature of around 30-40 K. Recently developed interface engineered junctions can be classified as junctions of this type. These junctions also raise an interesting problem in physics concerning the possibility of resonant tunneling of Cooper pairs via localized states in the barrier. From the viewpoint of practical applications, the improvement of the spread of the junction parameters is still a serious challenge to the present fabrication technology. Although interface engineered junctions seem to be most promising in this regard at present, 1σ spread of around 8% in the present fabrication technology is far from satisfactory for the fabrication of large-scale integrated circuits. The detailed understanding of the barrier formation mechanism in the interface engineered junction is indispensable not only for advancing this particular fabrication technology but also for improving other junction technology utilizing ramp-edge structures.

A 5-pole lumped element bandpass filter (BPF) of center frequency 264.05 MHz and fractional bandwidth (FBW) 0.76% is designed and fabricated using YBa2Cu3O7-d (YBCO) thin films deposited on both sides of a MgO substrate(40 mm 40 mm 0.5 mm). The return loss, minimum insertion loss and ripple were measured to be 20.0 dB, less than 0.1 dB and less than 0.1 dB at 70 K, respectively. These results verify both the compactness and low loss characteristics in the VHF band. The simulated frequency response, where the frequency dependences of inductance (L) and capacitance (C) elements and housing effect are taken into account, is in good agreement with the measured frequency response.

An efficient procedure is presented to determine the implicit exact solution of an arbitrary nonuniform transmission line (NTL), and its first order approximation (F. O. A. ) as an explicit expression. The method of the solution is based on the steplines approximation of the nonuniform transmission lines and quasi-TEM assumptions. Using steplines approximation the NTL is subdivided into a large number of uniform line segments (steps). Using time-domain approach and invoking the boundary conditions at the discontinuities of the adjacent steps, each step is modeled as continuous time domain linear filter characterized by a transfer function. The frequency domain transfer function of this filter is then obtained for linear termination networks. For very large number of steplines this transfer function approaches transfer function of the NTL. In the next step a F. O. A. , as an explicit expression of the exact response will be obtained. This F. O. A. is more suitable for very short transmission lines which is often the case in integrated circuits and some of printed circuit boards. Then, the F. O. A. of the ABCD matrix will be obtained.

In this paper, we describe an implementation of analog neural network system with on-line learning capability. A learning rule using the simultaneous perturbation is adopted. Compared with usage of the ordinary back-propagation method, we can easily implement the simultaneous perturbation learning rule. The neural system can monitor weight values and an error value. The exclusive OR problem and a simple function problem are shown.

This paper describes a digital delay-lock Loop (DLL) to which delta-sigma (Δ Σ) modulation technique is applied in order to reduce circuit elements. The DLL is evaluated in both transient and steady-state behavior by theoretical analysis, computer simulations and circuit experiments. Not deteriorated by the internally generated Δ Σ-modulation noise, the DLL shows good tracking performance in transient response and steady-state RMS jitter of phase error against additive white Gaussian noise. Using the proposed DLL most parts of receiving circuits are realized by digital integrated circuits. After realizing the circuit, power-line communication system with spread spectrum is possibly expected in a small size with low cost.

In our previous paper we presented a path-tracing method of multiple gate delay fault diagnosis in combinational circuits. In this paper, we propose an improved method that uses the ambiguous delay model. This delay model makes provision for parameter variations in the manufacturing process of ICs. For the effectiveness of the current method, we propose a timed 8-valued simulation and some new diagnostic rules. Furthermore, we introduce a preparatory process that speeds up diagnosis. Also, at the end of diagnosis, additional information from the results of the preparatory process makes it possible to distinguish between non-existent faults and undiagnosed faults.