The slope of transient waveform is dominated by the characteristics of the discharging (or charging) path, including the path topology, the sizes and the states of MOS transistors. The slope value of transient waveform can be obtained by calculating the equivalent RC time constant of the evaluated cluster circuit, and it can be obtained efficiently by traversing the tree recursively. However, bottleneck effect always exists in the charging/discharging path and plays an important role on the charging/discharging behavior of the output. If neglect the effect, the waveform approximation technique used in BTS will give rise to a larger error in some cases. Therefore, we propose an algorithm to solve this problem.

Accurate current analysis is required in circuit designs to analyze electromigration failure rate, power consumption, voltage drop, and so on. A charge-based current model for CMOS gates is presented in this paper. The current waveform of a CMOS gate during a transition consists of three components: one occurs when the input changes and the others exist only when the output changes. These three components are characterized by triangular pulses with four parameters which can be easily obtained after timing simulation. This model has been embedded into our switch-level timing simulator to generate the current waveform. The simulated current waveform helps solve the VLSI reliability problems due to electromigration and excess voltage drops in the power buses. When comparing the results obtained by using SPICE with those by our model, we find agreement, especially on the time points at which current pulses occur.