IEICE TRANSACTIONS on Fundamentals
A Single-Chip Stereo Audio Delta-Sigma A/D Converter with 117 dB Dynamic Range
Summary :
A 24-bit, 96 kHz stereo A/D converter (ADC) for DVD-audio has been developed. The single-chip integrates stereo delta-sigma modulators (Δ ΣM's), a voltage reference, and a decimation filter. A fourth-order cascaded Δ ΣM using a local feedback technique was employed to avoid overload without sacrificing noise performance. Low power switched-capacitor techniques were used for implementation. A two-stage decimation filter architecture that reduces digital switching noise was also developed. A merged multi-stage comb filter was used for the first stage, and a bit-serial finite-impulse-response (FIR) filter was used for the second stage. The 18.0 mm2 chip was fabricated in 0.6-µm CMOS with low threshold devices. Measured results show 117 dB A-weighted dynamic range in the 20 kHz passband, with 470 mW power dissipation at 5 V operation.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E83-A No.2 pp.243-251
- Publication Date
- 2000/02/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics)
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Ichiro FUJIMORI, "A Single-Chip Stereo Audio Delta-Sigma A/D Converter with 117 dB Dynamic Range" in IEICE TRANSACTIONS on Fundamentals,
vol. E83-A, no. 2, pp. 243-251, February 2000, doi: .
Abstract: A 24-bit, 96 kHz stereo A/D converter (ADC) for DVD-audio has been developed. The single-chip integrates stereo delta-sigma modulators (Δ ΣM's), a voltage reference, and a decimation filter. A fourth-order cascaded Δ ΣM using a local feedback technique was employed to avoid overload without sacrificing noise performance. Low power switched-capacitor techniques were used for implementation. A two-stage decimation filter architecture that reduces digital switching noise was also developed. A merged multi-stage comb filter was used for the first stage, and a bit-serial finite-impulse-response (FIR) filter was used for the second stage. The 18.0 mm2 chip was fabricated in 0.6-µm CMOS with low threshold devices. Measured results show 117 dB A-weighted dynamic range in the 20 kHz passband, with 470 mW power dissipation at 5 V operation.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e83-a_2_243/_p
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@ARTICLE{e83-a_2_243,
author={Ichiro FUJIMORI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A Single-Chip Stereo Audio Delta-Sigma A/D Converter with 117 dB Dynamic Range},
year={2000},
volume={E83-A},
number={2},
pages={243-251},
abstract={A 24-bit, 96 kHz stereo A/D converter (ADC) for DVD-audio has been developed. The single-chip integrates stereo delta-sigma modulators (Δ ΣM's), a voltage reference, and a decimation filter. A fourth-order cascaded Δ ΣM using a local feedback technique was employed to avoid overload without sacrificing noise performance. Low power switched-capacitor techniques were used for implementation. A two-stage decimation filter architecture that reduces digital switching noise was also developed. A merged multi-stage comb filter was used for the first stage, and a bit-serial finite-impulse-response (FIR) filter was used for the second stage. The 18.0 mm2 chip was fabricated in 0.6-µm CMOS with low threshold devices. Measured results show 117 dB A-weighted dynamic range in the 20 kHz passband, with 470 mW power dissipation at 5 V operation.},
keywords={},
doi={},
ISSN={},
month={February},}
Copy
TY - JOUR
TI - A Single-Chip Stereo Audio Delta-Sigma A/D Converter with 117 dB Dynamic Range
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 243
EP - 251
AU - Ichiro FUJIMORI
PY - 2000
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E83-A
IS - 2
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - February 2000
AB - A 24-bit, 96 kHz stereo A/D converter (ADC) for DVD-audio has been developed. The single-chip integrates stereo delta-sigma modulators (Δ ΣM's), a voltage reference, and a decimation filter. A fourth-order cascaded Δ ΣM using a local feedback technique was employed to avoid overload without sacrificing noise performance. Low power switched-capacitor techniques were used for implementation. A two-stage decimation filter architecture that reduces digital switching noise was also developed. A merged multi-stage comb filter was used for the first stage, and a bit-serial finite-impulse-response (FIR) filter was used for the second stage. The 18.0 mm2 chip was fabricated in 0.6-µm CMOS with low threshold devices. Measured results show 117 dB A-weighted dynamic range in the 20 kHz passband, with 470 mW power dissipation at 5 V operation.
ER -
English
