High-speed low-power matched filter plays an important role in the fast despreading of spread-signals in wideband code division multiple access (W-CDMA) mobile communications. In this paper, we describe the algorithm and the VLSI-architecture of a complex matched filter chip implemented by our proposed digital-controlled analog parallel operational circuits. The complex matched filter VLSI with variable taps from 4 to 128 is developed for despreading QPSK-modulated spread-signals for W-CDMA communications, which is fabricated by a 2-metal 0.8 µm CMOS technology. The dissipation power of the chip is 225 mW and 130 mW when it operates at the chip-rate of 20 MHz with the supply voltages of 3.0 V and 2.5 V, respectively, and it can be furthermore reduced to 62 mW at chip rate of 10 MHz when the supply voltage is lowered to 2.2 V. The 3-dB cut-off frequency of the fabricated chip is higher than 20 MHz for both 3.0 V and 2.5 V supplies. Comparing to pure digital matched filters, the massive and high-speed despreading operations of the spread-signals are directly carried out in analog domain. As a result, two high-speed analog-to-digital (A/D) converters operating at chip rate are omitted, the inner signal paths and the total dissipation power are greatly reduced.

Weighted summation (W-SUM) operation of multi-input signals plays an important role in signal processing, image compression and communication systems. Conventional digital LSI implementation for the massive high-speed W-SUM operations usually consumes a lot of power, and the power dissipation linearly increases with the operational frequencies. Analog or digital-analog mixed technology may provide a solution to this problem, but the large scale integration for analog circuits especially for digital-analog mixed circuits faces some difficulties in terms of circuit design, mixed-simulation, physical layout and anti-noises. To practically integrate large scale analog or digital-analog mixed circuits, the simplicity of the analog circuits are usually required. In this paper, we present a solution to realize the parallel W-SUM operations of multi-input analog signals based on our developed digital-controlled analog operational circuits. The major features of the proposed circuits include the simplicity in the circuitry architecture and the advantage in the dissipation power, which make it easy to be designed and to be integrated in large scale. To improve the design efficiency, a Top-Down design approach for mixed LSI implementation is proposed. The proposed W-SUM circuits and the Top-Down design approach have been practically used in the LSI implementation for a series of programmable finite impulse response (FIR) filters and matched filters applied in adaptive signal processing and the mobile communication systems based on the wideband code division multiple access (W-CDMA) technology.

A matched filter (Mf) based on analog filter technology for DS-CDMA mobile radio is presented. An experimental one-chip LSI of AMF is developed for measuring various areas of performance such as power consumption, cut-off frequency, and linearity. The measurements show that power consumption is only 110mW at a voltage supply of 3V and an operational clock frequency of 25 MHz. We implemented a RAKE combiner using experimental AMF LSI and measured the bit error rate (BER) performance of DS-CDMA signal transmission in a multipath fading environment.