Small loop gain and low crossover frequency result in poor dynamic performance of a single-loop output voltage controlled boost converter in continuous conduction mode. Multi-loop current control can improve the dynamic performance, however, the cost, size and weight of the circuit will also be increased. Sensorless multi-loop control solves the problems, however, the difficulty of the closed-loop characteristics evaluation will be severely aggravated, because there are more parameters in the loops, meanwhile, different from the single-loop, the relationships between the loop gains and closed-loop characteristics including audio susceptibility and output impedance are generally indirect for the multi-loop. Therefore, in this paper, a novel robust H∞ synthesis approach in the time-domain is proposed to design a sensorless controller for boost converters, which need not solve any algebraic Riccati equation or linear matrix inequalities, and most importantly, provides an approach to parameterizing the controller by an adjustable parameter. The adjustable parameter behaves like a ‘knob’ on the dynamic performance, consequently, which makes the closed-loop characteristics evaluation straightforward. A boost converter is used to verify the proposed synthesis approach. Simulations show the great convenience of the closed-loop characteristics evaluation. Practical experiments confirm the simulations.

This paper investigates the problem of scheduling parallel tasks" with consideration of communication cost on an m-processor system, where processors are assumed to be identical and tasks being scheduled are independent such that they can run on more than one processor simultaneously. Once a task is processed in parallel, its finish time will be speeded up, but communication cost will also be incurred and should be taken into account. To find a schedule with minimum finish time for the parallel tasks scheduling problem is NP-hard. Therefore, in this paper, we will propose a heuristic algorithm for this kind of problem and derive its performance bounds for two different cases of applications, respectively.

This paper illustrates a feasible health informatics domain knowledge management process which helps gather useful technology information and reduce many knowledge misunderstandings among engineers who have participated in the IBM mainframe rightsizing project at National Taiwan University (NTU) Hospital. We design an asynchronously sharing mechanism to facilitate the knowledge transfer and our health informatics domain knowledge management process can be used to publish and retrieve documents dynamically. It effectively creates an acceptable discussion environment and even lessens the traditional meeting burden among development engineers. An overall description on the current software development status is presented. Then, the knowledge management implementation of health information systems is proposed.

Given an odd prime q and an integer m ≤ q, an array-based parity-check matrix H(m,q) can be constructed for a quasi-cyclic low-density parity-check (LDPC) code C(m,q). For m=4 and q ≥ 11, we prove the stopping distance of H(4,q) is 10, which is equal to the minimum Hamming distance of the associated code C(4,q). In addition, a tighter lower bound on the stopping distance of H(m,q) is also given for m > 4 and q ≥ 11.

Accurate estimation of the state-of-charge is a crucial need for the battery, which is the most important power source in electric vehicles. To achieve better estimation result, an accurate battery model with optimum parameters is required. In this paper, a gradient-free optimization technique, namely tree seed algorithm (TSA), is utilized to identify specific parameters of the battery model. In order to strengthen the search ability of TSA and obtain more quality results, the original algorithm is improved. On one hand, the DE/rand/2/bin mechanism is employed to maintain the colony diversity, by generating mutant individuals in each time step. On the other hand, the control parameter in the algorithm is adaptively updated during the searching process, to achieve a better balance between the exploitation and exploration capabilities. The battery state-of-charge can be estimated simultaneously by regarding it as one of the parameters. Experiments under different dynamic profiles show that the proposed method can provide reliable and accurate estimation results. The performance of conventional algorithms, such as genetic algorithm and extended Kalman filter, are also compared to demonstrate the superiority of the proposed method in terms of accuracy and robustness.

This paper proposes an opamp-free solution to implement single-phase-clock controlled noise shaping in a SAR ADC. Unlike a conventional noise shaping SAR ADC, the proposal realizes noise shaping by charge redistribution, which is a passive technique. The passive implementation has high power efficiency. Meanwhile, since the proposal maintains the basic architecture and operation method of a traditional SAR ADC, it retains all the advantages of a SAR ADC. Furthermore, noise shaping helps to improve the performance of SAR ADC and relaxes its non-ideal effects. Designed in a 65-nm CMOS technology, the prototype realizes 58-dB SNDR based on an 8-bit C-DAC at 50-MS/s sampling frequency. It consumes 120.7-µW power from a 0.8-V supply and achieves a FoM of 14.8-fJ per conversion step.

High-speed low-power matched filter plays an important role in the fast despreading of spread-signals in wideband code division multiple access (W-CDMA) mobile communications. In this paper, we describe the algorithm and the VLSI-architecture of a complex matched filter chip implemented by our proposed digital-controlled analog parallel operational circuits. The complex matched filter VLSI with variable taps from 4 to 128 is developed for despreading QPSK-modulated spread-signals for W-CDMA communications, which is fabricated by a 2-metal 0.8 µm CMOS technology. The dissipation power of the chip is 225 mW and 130 mW when it operates at the chip-rate of 20 MHz with the supply voltages of 3.0 V and 2.5 V, respectively, and it can be furthermore reduced to 62 mW at chip rate of 10 MHz when the supply voltage is lowered to 2.2 V. The 3-dB cut-off frequency of the fabricated chip is higher than 20 MHz for both 3.0 V and 2.5 V supplies. Comparing to pure digital matched filters, the massive and high-speed despreading operations of the spread-signals are directly carried out in analog domain. As a result, two high-speed analog-to-digital (A/D) converters operating at chip rate are omitted, the inner signal paths and the total dissipation power are greatly reduced.

Weighted summation (W-SUM) operation of multi-input signals plays an important role in signal processing, image compression and communication systems. Conventional digital LSI implementation for the massive high-speed W-SUM operations usually consumes a lot of power, and the power dissipation linearly increases with the operational frequencies. Analog or digital-analog mixed technology may provide a solution to this problem, but the large scale integration for analog circuits especially for digital-analog mixed circuits faces some difficulties in terms of circuit design, mixed-simulation, physical layout and anti-noises. To practically integrate large scale analog or digital-analog mixed circuits, the simplicity of the analog circuits are usually required. In this paper, we present a solution to realize the parallel W-SUM operations of multi-input analog signals based on our developed digital-controlled analog operational circuits. The major features of the proposed circuits include the simplicity in the circuitry architecture and the advantage in the dissipation power, which make it easy to be designed and to be integrated in large scale. To improve the design efficiency, a Top-Down design approach for mixed LSI implementation is proposed. The proposed W-SUM circuits and the Top-Down design approach have been practically used in the LSI implementation for a series of programmable finite impulse response (FIR) filters and matched filters applied in adaptive signal processing and the mobile communication systems based on the wideband code division multiple access (W-CDMA) technology.

This paper presents the design of a multiple-standard 1080 high definition (HD) video decoder on a mixed-grained reconfigurable computing platform integrating coarse-grained reconfigurable processing units (RPUs) and FPGAs. The proposed RPU, including 16×16 multi-functional processing elements (PEs), is used to accelerate compute-intensive tasks in the video decoding. A soft-core-based microprocessor array is implemented on the FPGA and adopted to speed-up the dynamic reconfiguration of the RPU. Furthermore, a mail-box-based communication scheme is utilized to improve the communication efficiency between RPUs and FPGAs. By exploiting dynamic reconfiguration of the RPUs and static reconfiguration of the FPGAs, the proposed platform achieves scalable performances and cost trade-offs to support a variety of video coding standards, including MPEG-2, AVS, H.264, and HEVC. The measured results show that the proposed platform can support H.264 1080 HD video streams at up to 57 frames per second (fps) and HEVC 1080 HD video streams at up to 52fps under 250MHz, at the same time, it achieves a 3.6× performance gain over an industrial coarse-grained reconfigurable processor for H.264 decoding, and a 6.43× performance boosts over a general purpose processor based implementation for HEVC decoding.

This paper proposes a SAR-VCO hybrid 1-1 MASH ADC architecture, where a fully-passive 1st-order noise-shaping SAR ADC is implemented in the first stage to eliminate Op-amp. A VCO-based ADC quantizes the residue of the SAR ADC with one additional order of noise shaping in the second stage. The inter-stage gain error can be suppressed by a foreground calibration technique. The proposed ADC architecture is expected to accomplish 2nd-order noise shaping without Op-amp, which makes both high SNDR and low power possible. A prototype ADC is designed in a 65nm CMOS technology to verify the feasibility of the proposed ADC architecture. The transistor-level simulation results show that 75.7dB SNDR is achieved in 5MHz bandwidth at 60MS/s. The power consumption is 748.9µW under 1.0V supply, which results in a FoM of 14.9fJ/conversion-step.

The top-K sorting is a variant of sorting used heavily in applications such as database management systems. Recently, the use of field programmable gate arrays (FPGAs) to accelerate sorting operation has attracted the interest of researchers. However, existing hardware top-K sorting algorithms are either resource-intensive or of low throughput. In this paper, we present a resource-efficient top-K sorting architecture that is composed of L cascading sorting units, and each sorting unit is composed of P sorting cells. K=PL largest elements are produced when a variable length input sequence is processed. This architecture can operate at a high frequency while consuming fewer resources. The experimental results show that our architecture achieved a maximum 1.2x throughput-to-resource improvement compared to previous studies.

A complete analysis for the quantization noises and the reconstruction noises of the wavelet pyramid coding system is given. It is shown that in the (orthonormal) wavelet image coding system, there exists a simple and exact formula to compute the reconstruction mean-square-error (MSE) for any kind of quantization errors. Based on the noise analysis, an optimal bit allocation scheme which minimizes the system reconstruction distortion at a given rate is developed. The reconstruction distortion of a wavelet pyramid system is proved to be directly proportional to 2-2, where is a given bit rate. It is shown that, when the optimal bit allocation scheme is adopted, the reconstruction noises can be approximated to white noises. Particularly, it is shown that with only one known quantization MSE of a wavelet decomposition at any layer of the wavelet pyramid, all of the reconstruction MSE's and the quantization MSE's of the coding system can be easily calculated. When uniform quantizers are used, it is shown that at two successive layers of the wavelet pyramid, the optimal quantization step size is a half of its predecessor, which coincides with the resolution version of the wavelet pyramid decomposition. A comparison between wavelet-based image coding and some well-known traditional image coding methods is made by simulations, and the reasons why the wavelet-based image coding is superior to the traditional image coding are explained.

The conventional bilateral motion estimation (BME) for motion-compensated frame rate up-conversion (MC-FRUC) can avoid the problem of overlapped areas and holes but usually results in lots of inaccurate motion vectors (MVs) since 1) the MV of an object between the previous and following frames is more likely to have no temporal symmetry with respect to the target block of the interpolated frame and 2) the repetitive patterns existing in video frame lead to the problem of mismatch due to the lack of the interpolated block. In this paper, a new BME algorithm with a low computational complexity is proposed to resolve the above problems. The proposed algorithm incorporates multi-resolution search into BME, since it can easily utilize the MV consistency between two adjacent pyramid levels and spatial neighboring MVs to correct the inaccurate MVs resulting from no temporal symmetry while guaranteeing low computational cost. Besides, the multi-resolution search uses the fast wavelet transform to construct the wavelet pyramid, which not only can guarantee low computational complexity but also can reserve the high-frequency components of image at each level while sub-sampling. The high-frequency components are used to regularize the traditional block matching criterion for reducing the probability of mismatch in BME. Experiments show that the proposed algorithm can significantly improve both the objective and subjective quality of the interpolated frame with low computational complexity, and provide the better performance than the existing BME algorithms.

Light trail architecture is attracting attention as a new optical wavelength-division multiplexing network architecture that can be built with currently available devices and can achieve bandwidth allocation with granularity finer than a wavelength. Because a light trail is a shared medium, we need a medium access control (MAC) protocol to prevent collisions. Although MAC protocols using token passing can prevent collisions, the bandwidths of links that are located upstream of the token holding node are kept idle. We first propose a dynamic light trail splitting method for increasing throughput of a light trail by using such idle bandwidths. Our method splits a trail into upstream and downstream trails at the token holding node, and independent data transmission on the two trails are permitted. As a result, we expect that the split trail architecture will achieve higher throughput than the original non-split trail architecture. The degree of performance improvement with the split trail architecture depends on how appropriately we determine the upstream and downstream token holding times of every transmission node. Thus, we formulate a problem in which we optimize the token holding times to accommodate requested traffic volume as a linear programming problem. We then derive the throughput of the split trail architecture by solving the problem using the NUOPT solver and investigate the degree of improvement over the original architecture. In addition, we evaluate the end-to-end delay of the split trail architecture by simulation. According to numerical examples, the split trail architecture achieves 1) almost the same throughput as the original one for the worst-case traffic pattern where every transmission node sends data to the terminating node of the trail only, 2) about 1.6 times higher throughput for a uniform traffic pattern where every node pair requests the same traffic volume and an extremely unbalanced traffic pattern where only a few node pairs request huge traffic volume, 3) about 1.9 time higher throughput for the split trail architecture's good-case traffic pattern where every transmission node sends data to its adjacent downstream node only, and 4) the end-to-end delay enough to satisfy any application's QoS requirement according to ITU-T Recommendation Y.1541.

This CMOS transceiver IC exploits the superheterodyne architecture to implement a low-cost RF front-end with only 6.25 mm2 die area for IEEE 802.11b standard. The transceiver is implemented in 0.25 µm CMOS process with 2.7 V supply voltage, and achieves a -86 dBm 11 Mb/s receive sensitivity and a 2 dBm transmit output power.

The traditional RANSAC samples uniformly in the dataset which is not efficient in the task with rich prior information. This letter proposes GUISAC (Guided Sample Consensus), which samples with the guidance of various prior information. In image matching, GUISAC extracts seed points sets evenly on images based on various prior factors at first, then it incorporates seed points sets into the sampling subset with a growth function, and a new termination criterion is used to decide whether the current best hypothesis is good enough. Finally, experimental results show that the new method GUISAC has a great advantage in time-consuming than other similar RANSAC methods, and without loss of accuracy.

Most of current codesign tools or methodologies only support validation in the form of cosimulation and testing of design alternatives. The results of hardware-software codesign of a distributed system are often not verified, because they are not easily verifiable. In this paper, we propose a new formal coverification approach based on linear hybrid automata, and an algorithm for automatically converting codesign results to the linear hybrid automata framework. Our coverification approach allows automatic verification of real-time constraints such as hard deadlines. Another advantage is that the proposed approach is suitable for verifying distributed systems with arbitrary communication patterns and system architecture. The feasibility of our approach is demonstrated through several application examples. The proposed approach has also been successfully used in verifying deadline violations when there are inter-task communications between tasks with different period lengths.

Due to the large number of I/O's in a Ball-Grid-Array (BGA) package, routing becomes more and more an important work. A ring-based router for the BGA package is presented in this paper to interconnect each I/O pad of a chip to a corresponding ball distributed on the substrate area. The major phases for the router consist of layer assignment, topological routing, and physical routing. Using this router, we can generate an even distribution of planar and any-angle wires to improve manufacturing yield. We have also conducted various testing examples to verify the efficiency of this router. Experiments show that the router produces very good results, far better than the manual design, thus it can be applied to the practical packaging of integrated circuits.

In this paper, a new family of interconnection networks which we call the Incrementally Extensible Twisted Cube (IETQ) is proposed. The topology of this network is a novel generalization of the twisted cube. It inherits all the merits but without the limitations owned by a twisted cube. First, this proposed IETQ is incrementally extensible and can be adapted for use in any number of nodes; therefore, this network is particularly well suited for the design of a distributed communication network with an arbitrary number of nodes. Second, the vertex connectivity of IETQ is n. Measured by this vertex connectivity, we demonstrate that this network is optimally fault-tolerant . And it is almost regular, because the difference between the maximum and minimum degree of any node in an IETQ is at most one. A shortestpath routing algorithm for IETQ is proposed to generate path for any given pair of vertices in the network. Third, comparing with most of the other competitors, the diameter of this IETQ network is only half in size. This low diameter helps to reduce the internode communication delay. Moreover, IETQ also possesses the property of a pancyclic network. This attractive property would enable us to map rings of any length into the proposed network.

In this paper, we investigate the minimum-weight codewords of array LDPC codes C(m,q), where q is an odd prime and m ≤ q. Using some analytical approaches, the lower bound on the number of minimum-weight codewords of C(m,q) given by Kaji (IEEE Int. Symp. Inf. Theory, June/July 2009) is proven to be tight for m = 4 and q > 19. In other words, C(4,q) has 4q2(q-1) minimum-weight codewords for all q > 19. In addition, we show some interesting universal properties of the supports of generators of minimum-weight codewords of the code C(4,q)(q > 19).