IEICE TRANSACTIONS on Information
An Implementation of Multiple-Standard Video Decoder on a Mixed-Grained Reconfigurable Computing Platform
Summary :
This paper presents the design of a multiple-standard 1080 high definition (HD) video decoder on a mixed-grained reconfigurable computing platform integrating coarse-grained reconfigurable processing units (RPUs) and FPGAs. The proposed RPU, including 16×16 multi-functional processing elements (PEs), is used to accelerate compute-intensive tasks in the video decoding. A soft-core-based microprocessor array is implemented on the FPGA and adopted to speed-up the dynamic reconfiguration of the RPU. Furthermore, a mail-box-based communication scheme is utilized to improve the communication efficiency between RPUs and FPGAs. By exploiting dynamic reconfiguration of the RPUs and static reconfiguration of the FPGAs, the proposed platform achieves scalable performances and cost trade-offs to support a variety of video coding standards, including MPEG-2, AVS, H.264, and HEVC. The measured results show that the proposed platform can support H.264 1080 HD video streams at up to 57 frames per second (fps) and HEVC 1080 HD video streams at up to 52fps under 250MHz, at the same time, it achieves a 3.6× performance gain over an industrial coarse-grained reconfigurable processor for H.264 decoding, and a 6.43× performance boosts over a general purpose processor based implementation for HEVC decoding.
- Publication
- IEICE TRANSACTIONS on Information Vol.E99-D No.5 pp.1285-1295
- Publication Date
- 2016/05/01
- Publicized
- 2016/02/02
- Online ISSN
- 1745-1361
- DOI
- 10.1587/transinf.2015EDP7369
- Type of Manuscript
- PAPER
- Category
- Computer System
Authors
Leibo LIU
Tsinghua University
Dong WANG
Beijing Jiaotong University
Yingjie CHEN
Tsinghua University
Min ZHU
Tsinghua University
Shouyi YIN
Tsinghua University
Shaojun WEI
Tsinghua University
Keyword
Latest Issue
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Leibo LIU, Dong WANG, Yingjie CHEN, Min ZHU, Shouyi YIN, Shaojun WEI, "An Implementation of Multiple-Standard Video Decoder on a Mixed-Grained Reconfigurable Computing Platform" in IEICE TRANSACTIONS on Information,
vol. E99-D, no. 5, pp. 1285-1295, May 2016, doi: 10.1587/transinf.2015EDP7369.
Abstract: This paper presents the design of a multiple-standard 1080 high definition (HD) video decoder on a mixed-grained reconfigurable computing platform integrating coarse-grained reconfigurable processing units (RPUs) and FPGAs. The proposed RPU, including 16×16 multi-functional processing elements (PEs), is used to accelerate compute-intensive tasks in the video decoding. A soft-core-based microprocessor array is implemented on the FPGA and adopted to speed-up the dynamic reconfiguration of the RPU. Furthermore, a mail-box-based communication scheme is utilized to improve the communication efficiency between RPUs and FPGAs. By exploiting dynamic reconfiguration of the RPUs and static reconfiguration of the FPGAs, the proposed platform achieves scalable performances and cost trade-offs to support a variety of video coding standards, including MPEG-2, AVS, H.264, and HEVC. The measured results show that the proposed platform can support H.264 1080 HD video streams at up to 57 frames per second (fps) and HEVC 1080 HD video streams at up to 52fps under 250MHz, at the same time, it achieves a 3.6× performance gain over an industrial coarse-grained reconfigurable processor for H.264 decoding, and a 6.43× performance boosts over a general purpose processor based implementation for HEVC decoding.
URL: https://global.ieice.org/en_transactions/information/10.1587/transinf.2015EDP7369/_p
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@ARTICLE{e99-d_5_1285,
author={Leibo LIU, Dong WANG, Yingjie CHEN, Min ZHU, Shouyi YIN, Shaojun WEI, },
journal={IEICE TRANSACTIONS on Information},
title={An Implementation of Multiple-Standard Video Decoder on a Mixed-Grained Reconfigurable Computing Platform},
year={2016},
volume={E99-D},
number={5},
pages={1285-1295},
abstract={This paper presents the design of a multiple-standard 1080 high definition (HD) video decoder on a mixed-grained reconfigurable computing platform integrating coarse-grained reconfigurable processing units (RPUs) and FPGAs. The proposed RPU, including 16×16 multi-functional processing elements (PEs), is used to accelerate compute-intensive tasks in the video decoding. A soft-core-based microprocessor array is implemented on the FPGA and adopted to speed-up the dynamic reconfiguration of the RPU. Furthermore, a mail-box-based communication scheme is utilized to improve the communication efficiency between RPUs and FPGAs. By exploiting dynamic reconfiguration of the RPUs and static reconfiguration of the FPGAs, the proposed platform achieves scalable performances and cost trade-offs to support a variety of video coding standards, including MPEG-2, AVS, H.264, and HEVC. The measured results show that the proposed platform can support H.264 1080 HD video streams at up to 57 frames per second (fps) and HEVC 1080 HD video streams at up to 52fps under 250MHz, at the same time, it achieves a 3.6× performance gain over an industrial coarse-grained reconfigurable processor for H.264 decoding, and a 6.43× performance boosts over a general purpose processor based implementation for HEVC decoding.},
keywords={},
doi={10.1587/transinf.2015EDP7369},
ISSN={1745-1361},
month={May},}
Copy
TY - JOUR
TI - An Implementation of Multiple-Standard Video Decoder on a Mixed-Grained Reconfigurable Computing Platform
T2 - IEICE TRANSACTIONS on Information
SP - 1285
EP - 1295
AU - Leibo LIU
AU - Dong WANG
AU - Yingjie CHEN
AU - Min ZHU
AU - Shouyi YIN
AU - Shaojun WEI
PY - 2016
DO - 10.1587/transinf.2015EDP7369
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E99-D
IS - 5
JA - IEICE TRANSACTIONS on Information
Y1 - May 2016
AB - This paper presents the design of a multiple-standard 1080 high definition (HD) video decoder on a mixed-grained reconfigurable computing platform integrating coarse-grained reconfigurable processing units (RPUs) and FPGAs. The proposed RPU, including 16×16 multi-functional processing elements (PEs), is used to accelerate compute-intensive tasks in the video decoding. A soft-core-based microprocessor array is implemented on the FPGA and adopted to speed-up the dynamic reconfiguration of the RPU. Furthermore, a mail-box-based communication scheme is utilized to improve the communication efficiency between RPUs and FPGAs. By exploiting dynamic reconfiguration of the RPUs and static reconfiguration of the FPGAs, the proposed platform achieves scalable performances and cost trade-offs to support a variety of video coding standards, including MPEG-2, AVS, H.264, and HEVC. The measured results show that the proposed platform can support H.264 1080 HD video streams at up to 57 frames per second (fps) and HEVC 1080 HD video streams at up to 52fps under 250MHz, at the same time, it achieves a 3.6× performance gain over an industrial coarse-grained reconfigurable processor for H.264 decoding, and a 6.43× performance boosts over a general purpose processor based implementation for HEVC decoding.
ER -
English
