A Phase Compensation Technique without Capacitors for the CMOS Circuit with a Very Low Impedance Terminal
Summary :
A lower impedance terminal is necessary for an input terminal of current-mode circuits and an output terminal of voltage-mode circuits to reduce an error and distortion in analog signal processing. Thus, the CMOS circuit with a very low impedance terminal (VLIT circuit) is a useful analog building block to achieve the above purpose. The very low impedance terminal in the VLIT circuit is performed by a shunt-series feedback configuration. However, the feedback generates a problem of instability and/or oscillation at the same time. The problem can be removed by a phase compensation capacitor as known well, but the capacitor is not desirable for integrated circuits due to its large area. This paper proposes a new phase compensation technique for the VLIT circuit. The proposed technique does not need any capacitors to obtain a sufficient phase margin, and instead gives us the appropriate transistor sizes (Width and length of the gate). As a result, the VLIT circuit has an enough phase margin and operates stably.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E83-A No.2 pp.236-242
- Publication Date
- 2000/02/25
- Publicized
- Online ISSN
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- Type of Manuscript
- Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics)
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Eitake IBARAGI, Akira HYOGO, Keitaro SEKINE, "A Phase Compensation Technique without Capacitors for the CMOS Circuit with a Very Low Impedance Terminal" in IEICE TRANSACTIONS on Fundamentals,
vol. E83-A, no. 2, pp. 236-242, February 2000, doi: .
Abstract: A lower impedance terminal is necessary for an input terminal of current-mode circuits and an output terminal of voltage-mode circuits to reduce an error and distortion in analog signal processing. Thus, the CMOS circuit with a very low impedance terminal (VLIT circuit) is a useful analog building block to achieve the above purpose. The very low impedance terminal in the VLIT circuit is performed by a shunt-series feedback configuration. However, the feedback generates a problem of instability and/or oscillation at the same time. The problem can be removed by a phase compensation capacitor as known well, but the capacitor is not desirable for integrated circuits due to its large area. This paper proposes a new phase compensation technique for the VLIT circuit. The proposed technique does not need any capacitors to obtain a sufficient phase margin, and instead gives us the appropriate transistor sizes (Width and length of the gate). As a result, the VLIT circuit has an enough phase margin and operates stably.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e83-a_2_236/_p
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@ARTICLE{e83-a_2_236,
author={Eitake IBARAGI, Akira HYOGO, Keitaro SEKINE, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A Phase Compensation Technique without Capacitors for the CMOS Circuit with a Very Low Impedance Terminal},
year={2000},
volume={E83-A},
number={2},
pages={236-242},
abstract={A lower impedance terminal is necessary for an input terminal of current-mode circuits and an output terminal of voltage-mode circuits to reduce an error and distortion in analog signal processing. Thus, the CMOS circuit with a very low impedance terminal (VLIT circuit) is a useful analog building block to achieve the above purpose. The very low impedance terminal in the VLIT circuit is performed by a shunt-series feedback configuration. However, the feedback generates a problem of instability and/or oscillation at the same time. The problem can be removed by a phase compensation capacitor as known well, but the capacitor is not desirable for integrated circuits due to its large area. This paper proposes a new phase compensation technique for the VLIT circuit. The proposed technique does not need any capacitors to obtain a sufficient phase margin, and instead gives us the appropriate transistor sizes (Width and length of the gate). As a result, the VLIT circuit has an enough phase margin and operates stably.},
keywords={},
doi={},
ISSN={},
month={February},}
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TY - JOUR
TI - A Phase Compensation Technique without Capacitors for the CMOS Circuit with a Very Low Impedance Terminal
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 236
EP - 242
AU - Eitake IBARAGI
AU - Akira HYOGO
AU - Keitaro SEKINE
PY - 2000
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E83-A
IS - 2
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - February 2000
AB - A lower impedance terminal is necessary for an input terminal of current-mode circuits and an output terminal of voltage-mode circuits to reduce an error and distortion in analog signal processing. Thus, the CMOS circuit with a very low impedance terminal (VLIT circuit) is a useful analog building block to achieve the above purpose. The very low impedance terminal in the VLIT circuit is performed by a shunt-series feedback configuration. However, the feedback generates a problem of instability and/or oscillation at the same time. The problem can be removed by a phase compensation capacitor as known well, but the capacitor is not desirable for integrated circuits due to its large area. This paper proposes a new phase compensation technique for the VLIT circuit. The proposed technique does not need any capacitors to obtain a sufficient phase margin, and instead gives us the appropriate transistor sizes (Width and length of the gate). As a result, the VLIT circuit has an enough phase margin and operates stably.
ER -
English
