Majority logic is quite important for various applications such as fault tolerant systems, threshold logic, spectrum spread coding, and artificial neural networks. The circuit implementation of majority logic is difficult when the number of inputs becomes large because the number of transistors becomes huge and serious delay would occur. In this paper, we propose a new majority circuit with large fan-in. The circuit is composed of ordinary CMOS transistors and the total number of transistors is approximately only 4N, where N is the total number of inputs. We confirmed a correct operation by using HSPICE simulation. The yield of the proposed circuit was evaluated with respect to N under the variations of device parameters by using Monte Carlo simulation.

In this letter, we describe a low power current to time converter for wireless sensor networks. The proposed circuit has some advantages of high linearity and wide measurement range. From the evaluation using HSPICE with 0.18 µm CMOS device parameters, the output differential error for the input current variation is approximately 0.1 µs/nA under the condition that the current is varied from 100 nA to 500 nA. The idle power consumption is approximately zero.

A LC oscillator based upon the quadrature magnetic coupling to generate a mutual negative resistance (mu-R) is introduced. The topology offers enhanced optimum phase noise at low supply voltages by enabling extended circuit operation in the current-limited regime through the control of its mutual inductors' coupling factor, k. The principal operation of the mu-R oscillator is described and its comparison with the popular cross-coupled topology is discussed. The capability of the technique is demonstrated via design examples of 1.8 GHz oscillators. Simulations show that, by employing inductors with a self-inductance of 2 nH, a quality factor of about 7.5 and a coupling k=0.52, the mu-R oscillator exhibits the minimum phase noise of -142 dBc/Hz at 3 MHz-offset with 18 mA bias current and 2 V supply. This is 3-dB more than the minimum achievable phase noise in the cross-coupled oscillator with identical component parameters and supply voltage level.

Wired CDMA interface with adaptivity for interconnect capacitances is designed to receive transmitted data even under a wide variety of connection topologies. The variable gain amplifier (VGA) is one of key circuit blocks to realize the adaptivity for interconnect capacitances. The system level numerical simulations derive the VGA specifications that the required VGA gain range is from 0.37 to 2.0, which can be realized easily using a multiple-differential-pair technique.

The square-law characteristics of MOSFET in the saturation region have a parameter of threshold voltage VT. However, it introduces some complexities to the circuit design since it depends on kinds of MOS technology and cannot be controlled easily. In this paper, we show an equivalent MOSFET cell which has VT-programming capability and some application instances based on it. The simulation is carried out using CMOS 0.8 µm n-well technology and the results have shown the feasibility of the proposed structure.

A tail current source is often employed for many analog building blocks. It can limit the increase of excess power. It can also improve CMRR and PSRR. In this paper, we propose a very high output impedance tail current source for low voltage applications. The proposed tail current source has almost the same output impedance as the conventional cascode type tail current source in theory. Simulation results show that the output impedance of the proposed circuit becomes 1.28 GW at low frequencies. Applying the proposed circuit to a differential amplifier, the CMRR is enhanced by 66.7 dB, compared to the conventional differential amplifier. Moreover, the proposed circuit has the other excellent merit. The output stage of the proposed tail current source can operate at VDS(sat) and a quarter of VDS(sat) of the simple current source in theory and simulation, respectively. For example, in the simulation, when the reference current IREF is set to 100µA, the minimum voltage of the simple current source approximates 0.4 V, whereas that of the proposed current source approximates 0.1 V. Thus, the dynamic range can be enlarged by 0.3 V in this case. The value is still enough large value for low voltage applications. Hence, the proposed tail current source is suitable for low voltage applications.

A lower impedance terminal is necessary for an input terminal of current-mode circuits and an output terminal of voltage-mode circuits to reduce an error and distortion in analog signal processing. Thus, the CMOS circuit with a very low impedance terminal (VLIT circuit) is a useful analog building block to achieve the above purpose. The very low impedance terminal in the VLIT circuit is performed by a shunt-series feedback configuration. However, the feedback generates a problem of instability and/or oscillation at the same time. The problem can be removed by a phase compensation capacitor as known well, but the capacitor is not desirable for integrated circuits due to its large area. This paper proposes a new phase compensation technique for the VLIT circuit. The proposed technique does not need any capacitors to obtain a sufficient phase margin, and instead gives us the appropriate transistor sizes (Width and length of the gate). As a result, the VLIT circuit has an enough phase margin and operates stably.

This paper proposes a novel CMOS analog multiplier. As its significant merit, it is free from mobility reduction and body effect. Thus, the proposed multiplier is expected to have good linearity, comparing with conventional multipliers. Four transistors operating in the linear region constitute the input cell of the multiplier. Their sources and backgates are connected to the ground to cancel the body effect. eTheir gates are fixed to the same bias voltage to remove the effect of the mobility reduction. Input signals are applied to the drains of the input cell transistors through modified nullors. The simulation results show that THD is less than 0.8% for 0.6 V p-p input signal at 2.5-V supply voltage, and that the 3-dB bandwidth is up to about 13.3 MHz.

In this paper, a virtual-short circuit which consists of only two MOS transistors operated in the weak-inversion region is proposed. It has the advantages of almost zero power consumption, low voltage operation, small chip area, and no needlessness of bias voltages or currents. The second order effects, such as the device mismatch, the Early effect, and the temperature dependency of the circuit are analyzed in detail. Next, current-controlled and voltage-controlled current sources using the proposed virtual-short circuit are presented as applications. The performance of the proposed circuits is estimated using SPICE simulation with MOSIS 1. 2 µm CMOS device parameters. The results are reported on this paper.

This paper proposes a novel low power dissipation technique for a low voltage OTA. A conventional low power OTA with a class AB input stage is not suitable for a low voltage operation (1. 5 V supply voltages), because it uses composite transistors (referred to CMOS pair) which has a large threshold voltage. On the other hand, the tail-current type OTA needs a large tail-current value to obtain a sufficient input range at the expense of power dissipation. Therefore, the conventional tail-current type OTA has a trade-off between the input range and the power dissipation to the tail-current value. The trade-off can be eliminated by the proposed technique. The technique exploits negative feedback control including a current amplifier and a minimum current selecting circuit. The proposed technique was used on Wang's OTA to create another OTA, named Low Power Wang's OTA. Also, SPICE simulations are used to verify the efficiency of Low Power Wang's OTA. Although the static power of Low Power Wang's OTA is 122 µW, it has a sufficient input range, whereas conventional Wang's OTA needs 703 µW to obtain a sufficient input range. However, we can say that as the input signal gets larger, the power of Low Power Wang's OTA becomes larger.

This paper describes an MOS current-mode sample-and-hold (S/H) circuit that potentially operates with a sub-1. 5 V supply voltage, 20 MHz clock frequency, and less than 0. 1% linearity. A newly developed voltage-to-current converter suppresses the voltage change at an input terminal and achieves low-voltage operation with superior linearity. Sample switches are differentially placed at the inputs of a differential amplifier so that the feedthrough errors from switches cancel out. The MOS current-mode S/H circuit is designed and simulated using CMOS 0. 6 µm device parameters. Simulation results indicate that an operation with 20 MHz clock frequency, linearity error of less than 0. 1%, and 1 MHz input from a 1. 5 V power supply is achievable.

In this paper, a threshold voltage (VT) cancellation circuit for neuron-MOS (νMOS) analog circuits is described. By connecting the output terminal of this circuit with one of the input terminals of the νMOS transistor, cancellation ofVT is realized. The circuit has advantages of ground-referenced output and is insensitive to the fluctuation of bias and supply voltages. Second-order effects, such as the channel length modulation effect, the mobility reduction effect and device mismatch of the proposed circuit are analyzed in detail. Low-power and high-swing νMOS cascode current mirror is presented as an application. Performance of the proposed circuits is confirmed by HSPICE simulation with MOSIS 2. 0 µ p-well double-poly and double-metal CMOS device parameters.

Our study investigated the realization of a high-precision MOS current-mode circuit. Simple studies have implied that it is difficult to achieve a high signal-to-noise ratio (S/N) in a current-mode circuit. Since the signal voltage at the internal node is suppressed, the circuit is sensitive to various noise sources. To investigate this, we designed and fabricated a current-mode sample-and-hold circuit with a 3V power supply and a 20MHz clock speed, using a standard CMOS 0.6µm device process. The measured S/N reached 57dB and 59dB in sample mode, and 51dB and 54dB in sample-and-hold mode, with 115µA from a 3V power supply and 220µA from a 5V power supply of input currents and a 10MHz noise bandwidth. The S/N analysis based on an actual circuit was done taking device noise sources and the fold-over phenomena of noise in a sampled system into account. The calculation showed 66.9dB of S/N in sample mode and 59.5dB in sample-and-hold-mode with 115µA of input current. Both the analysis and measurement indicated that 60dB of S/N in sample mode with a 10MHz noise bandwidth is an achievable value for this sample-and-hold circuit. It was clear that the current-mode approach limits the S/N performance because of the voltage suppression method. This point should be further studied and discussed.

This paper describes an N-type and a P-type MOS cascode circuit based on the square-law characteristics of an MOS transistor in saturation region. The transconductance parameter ratios of an upper and a lower MOS transistor are set to be 1: n2 for the N-type MOS cascode circuit and n2: 1 for the P-type MOS cascode circuit. The N and P-type MOS cascode circuits are divided to four types by the difference of connections of input terminals. We consider the input-output relations of each type circuit. The second-order effects of the circuit such as channel length modulation effect, mobility reduction effect and device mismatch are analyzed. As applications, an analog voltage adder and a VT level shifter using MOS cascode circuits are presented. All of the proposed circuits are very simple and consist of only the N and P-type MOS cascode circuits. The proposed circuits aer confirmed by SPICE simulation with MOSIS 1.2µm CMOS process parameters.

This paper describes a novel input-free MOS VT extractor circuit. The circuit consists of a bias voltage block and a novel VT extractor block. The proposed VT extractor block has the advantages of the ground-referenced output, low influence of the nonideality, few numbers of transistors and no influence of the PMOS process. The PSpice simulations show the supply voltage range and the bias voltage range of the proposed circuit are wider than those of Johnson's or Wang's.

A MOS VCO which has improved linearity of oscillation frequency versus control voltage and has no 1/2 divider is studied. The improved VCO characteristic has been obtained by the use of only two additional transistors, one of which has a role of a load and another of which has a role of a control current source in a differential type delay cell.

Two types of novel nVT level shift circuits based on the square law characteristics of MOSFETs have been proposed. These circuits generate VIN+nVT or VIN-nVT (where VT is a threshold voltage), if the input voltage is applied as the VIN. These circuits can be widely used in MOSFET characterization, compensating VT effect, VT measurement, level shifting, etc. Type 1 is directly derived from the nVT-sift circuit proposed by Wang. Type 2 can reduce a total chip area than type 1 and has a wider input range. SPICE simulations show that the proposed circuits have a very wide input range and a small power consumption.

OTA (Operational Transconductance Amplifier) is a useful circuit in analog signal processing systems, especially in high-frequency applications. Important features of OTA are: infinite input impedance, electrically changeable transconductance (Gm), and much wider operation range without negative feedback such as in OPamp applications. The good linearity of OTA over wide input range is necessary to extend the application fields of OTA. Several techniques are developed to extend the input range with good linearity. In this paper, a highly-linear CMOS-OTA operating under 1 V power supply, is proposed. The concept of the proposed OTA is based on class-AB operation of two n-channel MOSFETs in the saturation region. By improving the input stage circuits, wide input range can be achieved. SPICE simulations are performed to verify the performance of the proposed OTA.