Design of a Novel MOS VT Extractor Circuit
Summary :
This paper describes a novel input-free MOS VT extractor circuit. The circuit consists of a bias voltage block and a novel VT extractor block. The proposed VT extractor block has the advantages of the ground-referenced output, low influence of the nonideality, few numbers of transistors and no influence of the PMOS process. The PSpice simulations show the supply voltage range and the bias voltage range of the proposed circuit are wider than those of Johnson's or Wang's.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E78-C No.9 pp.1306-1310
- Publication Date
- 1995/09/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- LETTER
- Category
- Electronic Circuits
Authors
Keyword
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Koichi TANNO, Okihiko ISHIZUKA, Zhen TANG, "Design of a Novel MOS VT Extractor Circuit" in IEICE TRANSACTIONS on Electronics,
vol. E78-C, no. 9, pp. 1306-1310, September 1995, doi: .
Abstract: This paper describes a novel input-free MOS VT extractor circuit. The circuit consists of a bias voltage block and a novel VT extractor block. The proposed VT extractor block has the advantages of the ground-referenced output, low influence of the nonideality, few numbers of transistors and no influence of the PMOS process. The PSpice simulations show the supply voltage range and the bias voltage range of the proposed circuit are wider than those of Johnson's or Wang's.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e78-c_9_1306/_p
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@ARTICLE{e78-c_9_1306,
author={Koichi TANNO, Okihiko ISHIZUKA, Zhen TANG, },
journal={IEICE TRANSACTIONS on Electronics},
title={Design of a Novel MOS VT Extractor Circuit},
year={1995},
volume={E78-C},
number={9},
pages={1306-1310},
abstract={This paper describes a novel input-free MOS VT extractor circuit. The circuit consists of a bias voltage block and a novel VT extractor block. The proposed VT extractor block has the advantages of the ground-referenced output, low influence of the nonideality, few numbers of transistors and no influence of the PMOS process. The PSpice simulations show the supply voltage range and the bias voltage range of the proposed circuit are wider than those of Johnson's or Wang's.},
keywords={},
doi={},
ISSN={},
month={September},}
Copy
TY - JOUR
TI - Design of a Novel MOS VT Extractor Circuit
T2 - IEICE TRANSACTIONS on Electronics
SP - 1306
EP - 1310
AU - Koichi TANNO
AU - Okihiko ISHIZUKA
AU - Zhen TANG
PY - 1995
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E78-C
IS - 9
JA - IEICE TRANSACTIONS on Electronics
Y1 - September 1995
AB - This paper describes a novel input-free MOS VT extractor circuit. The circuit consists of a bias voltage block and a novel VT extractor block. The proposed VT extractor block has the advantages of the ground-referenced output, low influence of the nonideality, few numbers of transistors and no influence of the PMOS process. The PSpice simulations show the supply voltage range and the bias voltage range of the proposed circuit are wider than those of Johnson's or Wang's.
ER -
English
