Recent high-speed bipolar technologies based on SICOS (Sidewall Base Contact Structure) transistors are reviewed. Bipolar device structures that include polysilicon are key technologies for improving circuit characteristics. As the characteristics of the upward operated SICOS transistors are close to those of downward transistors, they can easily be applied in memory cells which have near-perfect soft-error-immunity. Newly developed process technologies for making shallow base and emitter junctions to improve circuit performance are also reviewed. Finally, complementary bipolar technology for low-power and high-speed circuits using pnp transistors, and a quasi-drift base transistor structure suitable for below 0.1 µm emitters are discussed.

High speed GaAs ICs (Integrated Circutis) using FETs (Field Effect Transistors) are reported. As the fabricating techniques, ion implantation processes for both 0.5 µm and 0.2 µm gate FETs using W/Al refractory metal and 0.2 µm recessed gate process with MBE grown epitaxial wafers are shown. These fabrication processes are selected depending on the circuit speed and the integration level. The outline of the circuit design and the examples of ICs, which are developed for 10 Gb/s optical communication systems, are also shown with the obtained characteristics.

This paper discusses crystal-growth and device-design issues associated with the development of high-performance InP/InGaAs heretostructure bipolar transistors (HBTs). It is shown that a highly Si-doped n⁺-subcollector in the HBT structure causes anomalous Zn redistribution during metalorganic vapor phase epitaxial (MOVPE) growth. A thermodynamical model of and a useful solution to this big problem are presented. A novel hybrid structure consisting of an abrupt emitter-base heterojunction and a compositionally-graded base is shown to enhance nonequilibrium base transport and thereby increase current gain and cutoff frequency f_T. A double-heterostructure bipolar transistor (DHBT) with a step-graded InGaAsP collector can improve collector breakdown behavior without any speed penalty. We also elucidate the effect of emitter size shrinkage on high-frequency performance. Maximum oscillation frequency f_max in excess of 250 GHz is reported.

Device figure-of-merits for digital ICs are derived from analytical delay expressions for emitter-coupled logic and source-coupled FET logic inverters and are compared with the operating speeds of D-F/Fs reported in previous studies. We show that device figure-of-merits for baseband amplifiers are equivalent to those for digital ICs. The validity of device figure-of-merits are confirmed by measuring the bandwidth of the baseband amplifiers fabricated with AlGaAs/GaAs LBCTs.

A 0.1-µm gate-length GaAs MESFET technology is reported. A 48.3-GHz dynamic-frequency divider, and an amplifier with 20-dB gain and 17.5-GHz bandwidth are successfully fabricated by integrating over-100-GHz-cut-off frequency MESFETs using a new lightly-doped drain structure with a buried p-layer (BP-LDD) device structure.

In order to establish design and measurement technologies for an LSI that features high speed operation and low power dissipation, GaAs 2.5 Gbps 16 bit MUX/DEMUX LSIs have been successfully developed. DCFL is employed as a basic gate in order to reduce the power dissipation. For the purpose of achieving stable operation against the transistor parameter deviation, a timing design called clock tracking is employed. Moreover, to ensure accurate performance measurement, a new measurement system is introduced. The measurement system consists of an error rate detector (ERD), a pulse pattern generator (PPG) and a high speed tester (HST). The performances tested by the measurement system show the power consumptions of MUX and DEMUX LSIs are 1.35 W and 0.95 W. Input phase margin of DEMUX LSI is 290 degrees at 2.5 Gbps operation. The technologies obtained through development of these MUX/DEMUX LSIs are applicable to other high speed and low power LSIs.

We have developed a 15-Gbit/s 96-gate Si-bipolar gate array using 0.5-µm Si-bipolar technology, a sophisticated internal cell design, an I/O buffer design suitable for high-speed operation and high-frequency package technology. The decision circuit and 4 : 1 multiplexer fabricated on the gate array operate up to 15-Gbit/s and above 10-Gbit/s respectively. The data input sensitivity and the phase margin of the decision circuit are 53 mV_pp and 288 at 10-Gbit/s operation. This gate array promises to be useful in shortening the development period and lowering cost of 10-Gbit/s class IC's.

Millimeter-wave monolithic low noise amplifier modules using 0.15 µm AlGaAs/InGaAs/GaAs pseudomorphic HEMTs have been developed at V- and W-bands for the Advanced Microwave Scanning Radiometer. To achieve low noise and high gain of V-band single-stage and W-band two-stage monolithic amplifiers, a reactive matching method is employed in the design of input noise matching and output gain matching circuits based on the results of on-carrier S-parameter measurements up to 50 GHz and noise parameter measurements at 60 and 90 GHz. A V-band four-stage monolithic amplifier module has been mounted on a hermetically-sealed package with microstrip interface and has achieved a noise figure of 3 dB with a gain of 42.2 dB at 51 GHz. A W-band six-stage amplifier module has been mounted on a hermetically-sealed package with waveguide interface and has achieved a noise figure of 4.3 dB with a gain of 28.1 dB at 91 GHz. These results represent the best noise figure performance ever achieved by multi-stage monolithic low-noise amplifier modules.

This paper presents the fabrication and evaluation of a 60 GHz fully integrated MMIC one-chip receiver based on pseudomorphic InGaP/InGaAs/GaAs HEMT technology. The receiver consists of two 2-stage low-noise amplifiers (LNAs), a single-balanced active-gate mixer, a local oscillator (LO), and a buffer amplifier for the LO. The receiver has a conversion gain of greater than 17 dB from 60.2 GHz to 62.3 GHz, and the maximum conversion gain is 20 dB at 62.2 GHz. The noise figure of receiver is less than 6 dB in the IF range between 100 MHz and 1 GHz for a 61.536 GHz LO frequency, and the minimum noise figure is 4.9 dB at 1 GHz IF.

We propose an accurate FET model for microwave nonlinear circuit simulation, which has been modified from the Statz model. We have greatly enhanced the accuracy of both dc and capacitance expressions, especially in the knee voltage region where I_ds begins to saturate. In the expression of dc characteristics, our model improves the accuracy by incorporating the drain-source voltage dependence of pinch-off voltage, the gate-source voltage dependence of knee voltage, and the non-square dependence of drain current against the gate-source voltage. The non-square-root voltage dependence of gate capacitances is considered as well. All modifications are simple and the parameter extraction is kept as simple as that of the Statz model. By using this model, good agreement has been obtained between simulated and measured characteristics of a GaAs FET. For the dc characteristics and the S-parameters, each of estimated error is within 5% and 10%. The model accuracy has been verified by comparison of simulated and measured results of power amplifier performances over a wide range of operating conditions.

A direct calculation method of efficiency and power of FETs from d.c. characteristics determined by knee and breakdown voltages is proposed to make clear the requirements for knee and breakdown voltages of FETs under low-voltage operation of power amplifiers. It is shown from the calculation that the breakdown voltage has a greater effect on power and efficiency than the knee voltage and has to be three or more times of the operating voltage in order not to degrade efficiency under class-AB operation. A 3.3 V UHF-band 3-stage high efficiency and high power monolithic amplifier has been developed with the use of power FETs satisfying the requirements for knee and breakdown voltages under low-voltage operation. A power-added efficiency of 57.3% and a saturated output power of 31.8 dBm have been achieved for a drain voltage of 3.3 V in UHF-band. The direct calculation method of efficiency and power from d.c. characteristics, which can provide the required knee or breakdown voltage for a given efficiency, power, or bias conditions, is considered to be useful for developing power devices with various requirements for efficiency, power, and bias conditions.

A high efficiency and low voltage operation GaAs power amplifier module has been developed for the application to 1.5 GHz Japanese digital cellular phones. This paper summarizes the design method to increase efficiency and to reduce adjacent channel leakage power. Operated at a low drain bias voltage of 4.6 V, the power amplifier module delivers an output power of 1.5 W with 46% power-added efficiency and -52 dBs adjacent channel leakage power.

This paper describes 950 GHz power performance of double-doped AlGaAs/InGaAs/AlGaAs heterojunction field-effect transistors (HJFET) operated at a drain bias voltage ranging from 2.5 to 3.5 V. The developed 1.0 µm gatelength HJFET exhibited a maximum drain current (I_max) of 500 mA/mm, a transconductance (g_m) of 300 mS/mm, and a gate-to-drain breakdown voltage of 11 V. Operated at 3.0 V, a 17.5 mm gate periphery HJFET showed 1.4 W P_out and -50.3 dBc adjacent channel leakage power at a 50 kHz off-carrier frequency from 950 MHz with 50% PAE. Harmonic balance simulations revealed that the flat g_m characteristics of the HJFET with respect to gate bias voltage are effective to suppress intermodulation distortion under large signal operation. The developed HJFET has great potential for small-sized digital cellular power applications operated at a low DC supply voltage.

A GaAs defferential oscillator IC with on-chip LC resonator has been developed for suppressing the relative intensity noise (RIN) of a laser diode. The relationship between the Q-factor and minimum supply voltage for oscillation is fully described. In view of reducing the present LC resonator, we made use of BST (Barium Strontium Titanate) capacitor to make the resonator without increasing the chip area. The oscillation frequency is stable since it's determined by the geometry of the resonator. The experimentally fabricated oscillator IC achieved the output power of 12 dBm at the frequency of 600 MHz with voltage/current conditions of 2 V/20 mA. The present IC keeps quite stable RIN value less than -138 dB/Hz under the light-feedback condition up to 10%.

A wideband monolithic lossy match power amplifier having an LPF/HPF-combined interstage network has been developed. As an interstage network, it employs an LPF (Low-Pass Filter) including FET's drain capacitance, an HPF (High-Pass Filter) comprised of a dc blocking capacitor and a drain bias circuit, and a constant-resistance network for wideband impedance matching and transformation. With the use of this interstage network, a wide bandwidth of 6 to 16.5 GHz and an output power of 30.40.9 dBm have been achieved.

A 0.5 µm CMOS embedded function type gate array family with high speed modules was developed. This family has: an effective basic cell; high speed, compiled type metallized and diffused RAMs; PLL (Phase Locked Loop); and GTL (Gunning Transceiver Logic) to realize operation of over 100 MHz at 3.3 V. This paper describes the basic cell architecture and the compiled type metallized RAM. A divided MOS transistor type basic cell is effective for metallized modules such as metallized RAM and internal logic circuits. The appropriate basic cell size (height) can be decided from the viewpoints of the relationship between the number of usable basic cells and the basic cell height, and the logic circuit speed. Propagation delay time of the 2-input NAND is 200 ps at a standard load of fan out=2 and metal length=1.4 mm. For the universal ASIC, the compiled RAM is indispensable. Single port and multi-port metallized RAMs which are structured by using the basic cells are discussed. The new single port memory cell circuit which has a differential write and single end read operating method is introduced. This memory cell circuit can be realized using one basic cell. The diffused layer region of the NMOS transfer gates for the read operation is shared between neighbor memory cells. So, the capacitance of the bit line becomes smaller, and a high speed access time can be achieved. The measured access time of 1 kbits is 4.2 ns. The new multi-port memory cell circuits which have a single end write and single end read operating method are introduced. The read operating method is the same as that of the single port memory cell circuit. The access time shows very high speed operation comparable to that of the single port memory. This 3F (Flexible, Fast, and Friendly) ASIC family can be applied to high speed processors in workstations and graphics equipment.

The buried oxide nonintegrities, represented as the equivalent fixed oxide charge and interface trap densities at both the upper and lower interface of buried oxide, are evaluated for low-dose and high-dose SIMOX wafers, and their effects on device characteristics are investigated. The equivalent fixied oxide charge and trap densities at the lower interface, which are measured with buried oxide capacitors, are negligibly small in as-fabricated SIMOX wafers. This result enables us to make an analytical model of the parasitic drain/source-to-substrate capacitance in an SOI MOSFET, in which the effect of the depletion layer under the buried oxide is considered. The influence of thinner buried oxide and process-induced fixed oxide charge on the parasitic capacitance is explored with this model. The equivalent fixed oxide charge and trap densities at the upper interface are evaluated by the threshold voltage measurement in an SOI NMOSFET. The principle of this evaluation as well as the experimental technique are described in detail. The oxide charge and trap densities at the upper interface are higher than those at the lower interface for both SIMOX wafers. With a new model of the subthreshold slope based on a two-dimensional potential analysis the influence of the trap at the upper interface is discussed.

Silver is a fundamental material for electrical contact application. In spite of high electrical conductivity and economical advantage, silver surface is corroded easily by environment contained sulfide. A corrosion product as Ag₂S deteriorates the property of contact reliability. In order to examine contact reliability, the acceleration tests have been accepted widely in industries. In the present study, the acceleration factor of the contact reliability for the sulfide film on the surface of silver contact which was subject to the tarnish acceleration test was clarified in comparison with the film grown in a normal office environment. The accelerated environment based on the Japan Electric Industry Development Association (JEIDA) standard No.25 was adopted. This environment is consisted of air contained 3 ppm H₂S gas under 40, 85-95% RH. The growth rate of the sulfide film (Ag₂S) was evaluated by applying the ellipsometry analysis. In the results, it was found that growth of Ag₂S film of 500 in thickness in the normal office environment required corrosion time of 310³ h. This thickness of 500 caused increase in contact resistance of 0.1-1.0 (Ω). However, in the accelerated environment, corrosion time decreased to 1.7 h for same thickness. Therefore, the acceleration factor was obtained by comparison of these time as 1.810³ for the standard test of JEIDA.

A 0.15 µm T-shaped gate AlInAs/InGaAs high electron mobility transistor (HEMT) with an excellent RF performance has been developed using selective wet gate recess etching. The gate recess is formed by a pH-adjusted citric acid/NH₄OH/H₂O₂ mixture with an etching selectivity of more than 30 for InGaAs over AlInAs. The standard deviation of saturation drain current (I_dss) is as small as 3.2 mA for an average I_dss of 47 mA on a 3 inch diameter InP wafer. The etching time for recess formation is optimized and an ft of 130 GHz and an MSG of 10 dB at 60 GHz are obtained. The extremely low minimum noise figure (F_min) of 0.9 dB with an associated gain (Ga) of 7.0 dB has been achieved at 60 GHz for a SiON-passivated device. This noise performance is comparable to the lowest value of F_min ever reported for an AlInAs/InGaAs HEMT with a passivation film.

A photonic/video hybrid system for optical information processing by synthesis of the coherence function is proposed. Optical coherence function can be synthesized to have delta-function-like shape or notch shape by using direct frequency modulation of a laser diode with an appropriate waveform. Therefore, by choosing only the interference component in the interferometer, information processing functions can be obtained. The photonic/video hybrid system proposed provides a novel way to choose the interference component, which can improve the spatial resolution compared with our previous system with holographic technique. Selective extraction two-dimensional (2-D) information from a three-dimensional (3-D) object is successfully performed in basic experiments.

With a view to applying to the active matrix displays, micromechanical electrostatic switches having Si-N both-ends-fixed beam of size 1.4 µm by 23 µm grown with LP-CVD on Si wafer were studied about its kinetic switching characteristics, especially its switching speed and hysteresis behavior. Electrostatic beam sticking problems were improved with the additional inverse polarity and short duration pulse following on the turn-on signal. The switching beam deflection of 0.16 µm with the switching time of less than 100 nsec. was measured by tightly focused laser interferometric method. Observed turn-on threshold voltages were more than 30 V, and the on/off hysteresis widths were from one third to two thirds of its threshold voltage. The memory function was experimented for the 2 msec. long holding period with the hold voltage of 25 V following on the writing pulse with the duration of 2 µsec. and the amplitude of 32 V. Now, planarization process has been considered to imtroduce the contact electrodes that were not built-in for these experiments. Although conductive actual switches were not tested, with the obtained results, it seems that the micromechanical electrostatic switch has the large potentials as an active matrix element in display panel especially in electro-luminescent devices or field-emission devices.

The two-dimensional scattering problem of electromagnetic waves by a perfectly conducting wedge is analyzed by means of the Wiener-Hopf technique together with the formulation using the partition of scatterers. The Wiener-Hopf equations are derived on two complex planes. Investigating the mapping between these complex planes and introducing the appropriate functions which satisfy the edge condition of the wedge, the solutions of these equations are obtained by the decomposition procedure of functions. By deforming the integration path of the Fourier inverse transform, it is found that the representation of the scattered wave is in agreement with the integral representation using the Sommerfeld contours.

This paper describes a novel input-free MOS V_T extractor circuit. The circuit consists of a bias voltage block and a novel V_T extractor block. The proposed V_T extractor block has the advantages of the ground-referenced output, low influence of the nonideality, few numbers of transistors and no influence of the PMOS process. The PSpice simulations show the supply voltage range and the bias voltage range of the proposed circuit are wider than those of Johnson's or Wang's.

Mesa structures have been investigated to optimize a buried-heterostructure (BH) for a GaInAsP/InP surface-emitting (SE) laser regrown by metalorganic chemical vapor deposition (MOCVD), and it has been found that a square mesa top pattern of which the sides are at an angle of 45 to the 011 orientation is suitable. A 1.3-µm GaInAsP/InP square buried heterostructure (SBH) SE laser with this mesa structure has been demonstrated and low-threshold CW oscillation (threshold current I_th=0.45 mA) at 77 K and low-threshold room-temperature pulsed oscillation (I_th=12 mA) have been obtained.

A novel series-tapered nonlinear directional coupler is proposed to improve all-optical switching characteristics. Its switching characteristics are analyzed by using a beam propagation method based on the Galerkin's finite element technique. It is presented that the critical power of the series-tapered nonlinear directional coupler is smaller than conventional uniform symmetric and tapered nonlinear directional couplers.