IEICE TRANSACTIONS on Fundamentals
Design of a Sub-1. 5 V, 20 MHz, 0. 1% MOS Current-Mode Sample-and-Hold Circuit
Summary :
This paper describes an MOS current-mode sample-and-hold (S/H) circuit that potentially operates with a sub-1. 5 V supply voltage, 20 MHz clock frequency, and less than 0. 1% linearity. A newly developed voltage-to-current converter suppresses the voltage change at an input terminal and achieves low-voltage operation with superior linearity. Sample switches are differentially placed at the inputs of a differential amplifier so that the feedthrough errors from switches cancel out. The MOS current-mode S/H circuit is designed and simulated using CMOS 0. 6 µm device parameters. Simulation results indicate that an operation with 20 MHz clock frequency, linearity error of less than 0. 1%, and 1 MHz input from a 1. 5 V power supply is achievable.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E81-A No.2 pp.258-260
- Publication Date
- 1998/02/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section LETTER (Special Section on Analog Circuit Techniques in the Digital-Oriented Era)
- Category
Authors
Keyword
Latest Issue
Copyrights notice of machine-translated contents
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Cite this
Copy
Yasuhiro SUGIMOTO, Masahiro SEKIYA, "Design of a Sub-1. 5 V, 20 MHz, 0. 1% MOS Current-Mode Sample-and-Hold Circuit" in IEICE TRANSACTIONS on Fundamentals,
vol. E81-A, no. 2, pp. 258-260, February 1998, doi: .
Abstract: This paper describes an MOS current-mode sample-and-hold (S/H) circuit that potentially operates with a sub-1. 5 V supply voltage, 20 MHz clock frequency, and less than 0. 1% linearity. A newly developed voltage-to-current converter suppresses the voltage change at an input terminal and achieves low-voltage operation with superior linearity. Sample switches are differentially placed at the inputs of a differential amplifier so that the feedthrough errors from switches cancel out. The MOS current-mode S/H circuit is designed and simulated using CMOS 0. 6 µm device parameters. Simulation results indicate that an operation with 20 MHz clock frequency, linearity error of less than 0. 1%, and 1 MHz input from a 1. 5 V power supply is achievable.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e81-a_2_258/_p
Copy
@ARTICLE{e81-a_2_258,
author={Yasuhiro SUGIMOTO, Masahiro SEKIYA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Design of a Sub-1. 5 V, 20 MHz, 0. 1% MOS Current-Mode Sample-and-Hold Circuit},
year={1998},
volume={E81-A},
number={2},
pages={258-260},
abstract={This paper describes an MOS current-mode sample-and-hold (S/H) circuit that potentially operates with a sub-1. 5 V supply voltage, 20 MHz clock frequency, and less than 0. 1% linearity. A newly developed voltage-to-current converter suppresses the voltage change at an input terminal and achieves low-voltage operation with superior linearity. Sample switches are differentially placed at the inputs of a differential amplifier so that the feedthrough errors from switches cancel out. The MOS current-mode S/H circuit is designed and simulated using CMOS 0. 6 µm device parameters. Simulation results indicate that an operation with 20 MHz clock frequency, linearity error of less than 0. 1%, and 1 MHz input from a 1. 5 V power supply is achievable.},
keywords={},
doi={},
ISSN={},
month={February},}
Copy
TY - JOUR
TI - Design of a Sub-1. 5 V, 20 MHz, 0. 1% MOS Current-Mode Sample-and-Hold Circuit
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 258
EP - 260
AU - Yasuhiro SUGIMOTO
AU - Masahiro SEKIYA
PY - 1998
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E81-A
IS - 2
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - February 1998
AB - This paper describes an MOS current-mode sample-and-hold (S/H) circuit that potentially operates with a sub-1. 5 V supply voltage, 20 MHz clock frequency, and less than 0. 1% linearity. A newly developed voltage-to-current converter suppresses the voltage change at an input terminal and achieves low-voltage operation with superior linearity. Sample switches are differentially placed at the inputs of a differential amplifier so that the feedthrough errors from switches cancel out. The MOS current-mode S/H circuit is designed and simulated using CMOS 0. 6 µm device parameters. Simulation results indicate that an operation with 20 MHz clock frequency, linearity error of less than 0. 1%, and 1 MHz input from a 1. 5 V power supply is achievable.
ER -
English
