This paper examines the design considerations for an opamp to be used in a low-power consumption LCD driver IC: (1) slew rate enhancement suitable for a rail-to-rail input stage; (2) improved phase compensation with reduced compensation capacitance; and (3) limitation of instantaneous current consumption. The experimental results support our opamp design approach and indicate the feasibility of a 10 µA quiescent current opamp.

This paper proposes a novel low power dissipation technique for a low voltage OTA. A conventional low power OTA with a class AB input stage is not suitable for a low voltage operation (1. 5 V supply voltages), because it uses composite transistors (referred to CMOS pair) which has a large threshold voltage. On the other hand, the tail-current type OTA needs a large tail-current value to obtain a sufficient input range at the expense of power dissipation. Therefore, the conventional tail-current type OTA has a trade-off between the input range and the power dissipation to the tail-current value. The trade-off can be eliminated by the proposed technique. The technique exploits negative feedback control including a current amplifier and a minimum current selecting circuit. The proposed technique was used on Wang's OTA to create another OTA, named Low Power Wang's OTA. Also, SPICE simulations are used to verify the efficiency of Low Power Wang's OTA. Although the static power of Low Power Wang's OTA is 122 µW, it has a sufficient input range, whereas conventional Wang's OTA needs 703 µW to obtain a sufficient input range. However, we can say that as the input signal gets larger, the power of Low Power Wang's OTA becomes larger.

This paper describes an MOS current-mode sample-and-hold (S/H) circuit that potentially operates with a sub-1. 5 V supply voltage, 20 MHz clock frequency, and less than 0. 1% linearity. A newly developed voltage-to-current converter suppresses the voltage change at an input terminal and achieves low-voltage operation with superior linearity. Sample switches are differentially placed at the inputs of a differential amplifier so that the feedthrough errors from switches cancel out. The MOS current-mode S/H circuit is designed and simulated using CMOS 0. 6 µm device parameters. Simulation results indicate that an operation with 20 MHz clock frequency, linearity error of less than 0. 1%, and 1 MHz input from a 1. 5 V power supply is achievable.

Recently fiber optic links have been applied to radio signal distribution networks and also to signal feeder networks for phased array antennas, because they are able to offer wide bandwidth for achieving the high bit-rates and large capacity needed in the multimedia age. In these networks, a great many modules are needed to convert optical signals to radio signals. In order to reduce the complexity and cost of these modules, direct optical control techniques, which inject optical signals directly into microwave circuits, are very attractive. Thus, this paper proposes a novel optical control technique using tunable inductance circuits. This technique employs direct illumination as a means of optically tuning the inductance. Since the inductance value is inversely proportional to the square of the transconductance, it varies widely when the FET is directly illuminated. With direct illumination, the measured inductance variation in an experimental inductance circuit built with Pseudomorphic AlGaAs/InGaAs/GaAs HEMTs is more than 20 % from 0.5 to 2 GHz. As an application, a direct optically controlled oscillator was fabricated. The measured optical tuning range of the oscillation frequency is more than 19 % with an output power of -51 dBm. This is a promising technique for a variety of devices, including optically controlled oscillators, filters, phase shifters, and active antennas.

A current-to-frequency converter using switched-current (SI) circuits is proposed. The SI integrator with a hold-and-reset switch can control integration by the output signals. In the proposed circuit the oscillation frequency can be controlled by the input current, and the circuit is operated in the current domain. This is verified by HSPICE simulations.

Fundamental nonlinear filters including M-filters and order statistic filters are formulated generally by the maximum a-posteriori (MAP) estimation and some filters are derived with the aid of the Bayes formula. This MAP-filters reduces to M-filters if a-priori probability distribution is uniform, while the rank filters are derived when a-priori bias exists in the MAP estimation. This MAP-filters are implemented with an analog electronic circuit and the log-likelihood is shown to be a Liapunov function for the dynamics of this circuit.

In this paper, a threshold voltage (VT) cancellation circuit for neuron-MOS (νMOS) analog circuits is described. By connecting the output terminal of this circuit with one of the input terminals of the νMOS transistor, cancellation ofVT is realized. The circuit has advantages of ground-referenced output and is insensitive to the fluctuation of bias and supply voltages. Second-order effects, such as the channel length modulation effect, the mobility reduction effect and device mismatch of the proposed circuit are analyzed in detail. Low-power and high-swing νMOS cascode current mirror is presented as an application. Performance of the proposed circuits is confirmed by HSPICE simulation with MOSIS 2. 0 µ p-well double-poly and double-metal CMOS device parameters.

We have studied the methods to operate single electron circuits with high reliability at room temperature. By simulation, we have numerically analyzed the error mechanisms of the room-temperature operation of a 2-gate electron pump as a fundamental single electron element circuit. We have found from the results that under the room temperature condition where the ratio of the electrostatic energy to the thermal energy for a transition electron is not so large, the minimum operation error probability is obtained at the specific gate sweep time when the circuit is operated with ramp-waveform control voltages. The analyses indicate that in the shorter sweep time range, the error probability increases because the gate voltage has changed before the significant electron transition occurs, and that in the longer sweep time range, the error probability also increases due to undesired-single-transition events. The optimum sweep time is estimated statically with the relationship between desired- and undesired-single-transition rates as a function of control gate voltages. Using the optimum condition, the operation reliability is expected to be improved by a factor of 100. This estimation method has been also confirmed by the time-dependent Monte-Carlo simulation.

The basic operation characteristics of an asymmetric turnstile which transfers each electron one by one in one direction is described. A novel single electron counter circuit consisting of the asymmetric turnstiles, a load capacitor and an inverter which counts the number of high inputs is proposed. Monte Carlo circuit simulations reveal that the gate clock time of the counter circuit should be long enough to achieve allowable minimum error rate. The counter circuit implementing asymmetric single electron turnstiles is demonstrated to be applicable to a noise reduction system, a Winner-Take-All circuit and an artificial neuron circuit.

An econominal implementation of a chaos circuit onto the hardware is an important subject. In this letter, a two-dimensional digital chaos circuit realizing a Henon map is designed. Concerning the attractor and the bifurcation diagram of the proposed circuit, numerical simulations are performed to confirm the validity of the circuit algorithm. Furthermore, the proposed digital chaos circuit is designed by Verilog-HDL (Hardware Description Language). The proposed digital chaos circuit can be implemented into the form of the FPGA (Field Programmable Gate Array).

We propose a new method for verifying synchronous circuits using the Boyer-Moore Theorem Prover (BMTP) based on an efficient use of induction. The method contains two techniques. The one is the representation method of signals. Each signal is represented not as a waveform, but as a time parameterized function. The other is the mechanical transformation of the circuit description. A simple description of the logical connection of the components of a circuit is transformed into such a form that is not only acceptable as a definition of BMTP but also adequate for applying induction. We formalize the method and show that it realizes an efficient proof.

This paper proposes an architecture for circuit construction for developing single-electron integrated circuits based on majority logic. The majority logic gate circuit proposed consists of a capacitor array for input summation and a single-electron inverter for threshold operation. It accepts an odd number of inputs and produces the corresponding output on the basis of the principle of majority decision; it produces an output of logic "1" if the majority of the inputs is 1, and an output of "0" if the majority is 0. By combining the proposed majority gate circuits, various subsystems can be constructed with a smaller number of devices than that of Boolean-based construction. An adder and a parity generator are designed as examples. It is shown by computer simulation that the designed subsystems produce the correct logic operations. The operation error induced by thermal agitation is also estimated.

This paper proposes a method of constructing single-electron logic subsystems on the basis of the binary decision diagram (BDD). Sample subsystems, an adder and a comparator, are designed by combining single-electron BDD devices. It is demonstrated by computer simulation that the designed subsystems successfully produce, through pipelined processing, an output data flow in response to the input data flow. The operation error caused by thermal agitation is estimated. An output interface for converting single-electron transport into binary-voltage signals is also designed.

The efficiency and reliability of an ultrasonic motor, operating in longitudinal-torsional degenerate-mode, are investigated. It is essential to miniaturize both longitudinal and torsional mode piezoelectric ceramic elements, in order to produce low-cost ultrasonic motors, and to realize a motor with low battery power consumption. The ultrasonic motor is designed with an accurate mechanical equivalent circuit, which can produce high design precision notwithstanding low computation cost. It is important in this design that the resonant frequencies of longitudinal mode and torsional mode coincide with each other under the pertinent rotor pressing force and longitudinal and torsional mode piezoelectric ceramic elements are located in the vibration nodes for the longitudinal mode and the torsional mode, respectively. As a result, the fabricated motor, whose rotor diameter was 12 mm, produced 480 r.p.m. no-load revolution speed, 0.55 kgfcm maximum torque, 50% maximum efficiency, 2.5 W consumed power and a lifetime over 1000 hours with continuous rotation.

An experimental latch circuit is fabricated by using a 0.35µm MT-CMOS technology. This latch circuit has a volume smaller by 30%, a delay time shorter by 10%, and has an active power consumption smaller by 10% over those of a conventional MT-CMOS circuit. Furthermore, at a operation frequency of 100 MHz, an SRAM employing this IPS scheme has a standby current which is 0.4% of SRAM's without using IPS scheme.

A processor allocation scheme for mesh computers greatly affects their system utilization. The performance of an allocation scheme is largely dependent on its ability to detect available submeshes. We propose a new type of submesh, called a link-disjoint submesh, for processor allocation in mesh computers. This type of submesh increases the submesh recognition capability of an allocation scheme. A link-disjoint submesh is not a contiguous submesh as in the previous scheme, but this submesh still has no common communication link with any other submesh. When wormhole routing or circuit switching is used, the communication delay caused by non-contiguous processor allocation is minor. Through simulation, the performance of our scheme is measured and compared to the previous schemes in terms of such parameters as finish time and system utilization. It is shown through simulation that the link-disjoint submesh increases the performance of an allocation scheme.

Time-related jitters caused by small noise voltage due to electromagnetic noise induce malfunction of digital equipment. The jitters increase with not only magnitude of the noise but also resonance of digital circuits in the equipment. In this report, we proposes a linear equivalent circuit model of a digital CMOS gate for analyzing circuit resonance and verifies the validity of the model.

Recently, progress has been made in the area of electrical modeling of conductors embedded in arbitrary dielectrics using circuit oriented techniques. These models usually occur in conjunction with VLSI type circuits. Many different applications exist today for such models in the EMI, EIP (Electrical Interconnect and Package) analysis as well as for the microwave circuit area. Practical problems involve a multitude of hardware components and they demand a wide spectrum of both time as well as frequency domain solution techniques. In this paper we consider circuit oriented techniques for the solution of these problems. Specifically, we give an outline of the three dimensional Partial Element Equivalent Circuit (PEEC) full wave modeling approach and review the recent progress in this area.

The purpose of this report is to predict far-field EMI spectrum emitted from a signal line on a digital PCB based on near-field EMI measurement. The relation between near magnetic field and far electric field is shown. A method of predicting far electric field from near magnetic field is proposed. Current flowing along a signal line is calculated from measured near magnetic field. Far electric field is estimated from the current. Measurement and prediction of EM emission are carried out using a simple PCB. The result of prediction and measurement of far-field EMI spectrum coincide within the error of 3 dB.

This paper analyzes mechanisms of radiated emissions from multilayer printed circuit boards (PCBs) and presents a model to describe the characteristics of such radiation. The radiation mechanism from a four-layer PCB, including the internal power and ground planes, is investigated using a time-domain magnetic field measurement near the PCB. Measurement of the waveform indicates that the main source of radiation is in the power distribution planes. To investigate the characteristics of the radiation from the power distribution, the S21s of the board are measured; the board impedance and the transmission characteristics of the power distribution planes are found to be directly related to the S21 between the two points in the board. The results indicate that the power distribution acts as a transmission line at frequencies higher than 100 MHz. A model that can explain well the radiation properties of these planes treats them as a parallel-plate transmission line interconnected by decoupling circuit comprising a decoupling capacitor and interconnect inductance. From the transmission line theory it is deduced that the line resonance gives rise to strong radiated emissions. The interconnect inductance is an important factor in determining the radiation characteristics.