IEICE TRANSACTIONS on Electronics
Single-Electron Majority Logic Circuits
Summary :
This paper proposes an architecture for circuit construction for developing single-electron integrated circuits based on majority logic. The majority logic gate circuit proposed consists of a capacitor array for input summation and a single-electron inverter for threshold operation. It accepts an odd number of inputs and produces the corresponding output on the basis of the principle of majority decision; it produces an output of logic "1" if the majority of the inputs is 1, and an output of "0" if the majority is 0. By combining the proposed majority gate circuits, various subsystems can be constructed with a smaller number of devices than that of Boolean-based construction. An adder and a parity generator are designed as examples. It is shown by computer simulation that the designed subsystems produce the correct logic operations. The operation error induced by thermal agitation is also estimated.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E81-C No.1 pp.42-48
- Publication Date
- 1998/01/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Issue on Technology Challenges for Single Electron Devices)
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Hiroki IWAMURA, Masamichi AKAZAWA, Yoshihito AMEMIYA, "Single-Electron Majority Logic Circuits" in IEICE TRANSACTIONS on Electronics,
vol. E81-C, no. 1, pp. 42-48, January 1998, doi: .
Abstract: This paper proposes an architecture for circuit construction for developing single-electron integrated circuits based on majority logic. The majority logic gate circuit proposed consists of a capacitor array for input summation and a single-electron inverter for threshold operation. It accepts an odd number of inputs and produces the corresponding output on the basis of the principle of majority decision; it produces an output of logic "1" if the majority of the inputs is 1, and an output of "0" if the majority is 0. By combining the proposed majority gate circuits, various subsystems can be constructed with a smaller number of devices than that of Boolean-based construction. An adder and a parity generator are designed as examples. It is shown by computer simulation that the designed subsystems produce the correct logic operations. The operation error induced by thermal agitation is also estimated.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e81-c_1_42/_p
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@ARTICLE{e81-c_1_42,
author={Hiroki IWAMURA, Masamichi AKAZAWA, Yoshihito AMEMIYA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Single-Electron Majority Logic Circuits},
year={1998},
volume={E81-C},
number={1},
pages={42-48},
abstract={This paper proposes an architecture for circuit construction for developing single-electron integrated circuits based on majority logic. The majority logic gate circuit proposed consists of a capacitor array for input summation and a single-electron inverter for threshold operation. It accepts an odd number of inputs and produces the corresponding output on the basis of the principle of majority decision; it produces an output of logic "1" if the majority of the inputs is 1, and an output of "0" if the majority is 0. By combining the proposed majority gate circuits, various subsystems can be constructed with a smaller number of devices than that of Boolean-based construction. An adder and a parity generator are designed as examples. It is shown by computer simulation that the designed subsystems produce the correct logic operations. The operation error induced by thermal agitation is also estimated.},
keywords={},
doi={},
ISSN={},
month={January},}
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TY - JOUR
TI - Single-Electron Majority Logic Circuits
T2 - IEICE TRANSACTIONS on Electronics
SP - 42
EP - 48
AU - Hiroki IWAMURA
AU - Masamichi AKAZAWA
AU - Yoshihito AMEMIYA
PY - 1998
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E81-C
IS - 1
JA - IEICE TRANSACTIONS on Electronics
Y1 - January 1998
AB - This paper proposes an architecture for circuit construction for developing single-electron integrated circuits based on majority logic. The majority logic gate circuit proposed consists of a capacitor array for input summation and a single-electron inverter for threshold operation. It accepts an odd number of inputs and produces the corresponding output on the basis of the principle of majority decision; it produces an output of logic "1" if the majority of the inputs is 1, and an output of "0" if the majority is 0. By combining the proposed majority gate circuits, various subsystems can be constructed with a smaller number of devices than that of Boolean-based construction. An adder and a parity generator are designed as examples. It is shown by computer simulation that the designed subsystems produce the correct logic operations. The operation error induced by thermal agitation is also estimated.
ER -
English
