Linear Equivalent Circuit of a Digital Gate for Characterization of Malfunction Mechanism
Summary :
Time-related jitters caused by small noise voltage due to electromagnetic noise induce malfunction of digital equipment. The jitters increase with not only magnitude of the noise but also resonance of digital circuits in the equipment. In this report, we proposes a linear equivalent circuit model of a digital CMOS gate for analyzing circuit resonance and verifies the validity of the model.
- Publication
- IEICE TRANSACTIONS on Communications Vol.E80-B No.11 pp.1652-1653
- Publication Date
- 1997/11/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section LETTER (Special Issue on EMC Implications of Densely Mounted Electronic Devices)
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Naoki KAGAWA, Osami WADA, Ryuji KOGA, "Linear Equivalent Circuit of a Digital Gate for Characterization of Malfunction Mechanism" in IEICE TRANSACTIONS on Communications,
vol. E80-B, no. 11, pp. 1652-1653, November 1997, doi: .
Abstract: Time-related jitters caused by small noise voltage due to electromagnetic noise induce malfunction of digital equipment. The jitters increase with not only magnitude of the noise but also resonance of digital circuits in the equipment. In this report, we proposes a linear equivalent circuit model of a digital CMOS gate for analyzing circuit resonance and verifies the validity of the model.
URL: https://global.ieice.org/en_transactions/communications/10.1587/e80-b_11_1652/_p
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@ARTICLE{e80-b_11_1652,
author={Naoki KAGAWA, Osami WADA, Ryuji KOGA, },
journal={IEICE TRANSACTIONS on Communications},
title={Linear Equivalent Circuit of a Digital Gate for Characterization of Malfunction Mechanism},
year={1997},
volume={E80-B},
number={11},
pages={1652-1653},
abstract={Time-related jitters caused by small noise voltage due to electromagnetic noise induce malfunction of digital equipment. The jitters increase with not only magnitude of the noise but also resonance of digital circuits in the equipment. In this report, we proposes a linear equivalent circuit model of a digital CMOS gate for analyzing circuit resonance and verifies the validity of the model.},
keywords={},
doi={},
ISSN={},
month={November},}
Copy
TY - JOUR
TI - Linear Equivalent Circuit of a Digital Gate for Characterization of Malfunction Mechanism
T2 - IEICE TRANSACTIONS on Communications
SP - 1652
EP - 1653
AU - Naoki KAGAWA
AU - Osami WADA
AU - Ryuji KOGA
PY - 1997
DO -
JO - IEICE TRANSACTIONS on Communications
SN -
VL - E80-B
IS - 11
JA - IEICE TRANSACTIONS on Communications
Y1 - November 1997
AB - Time-related jitters caused by small noise voltage due to electromagnetic noise induce malfunction of digital equipment. The jitters increase with not only magnitude of the noise but also resonance of digital circuits in the equipment. In this report, we proposes a linear equivalent circuit model of a digital CMOS gate for analyzing circuit resonance and verifies the validity of the model.
ER -
English
