IEICE TRANSACTIONS on Electronics
A Low Power Data Storage Circuit with an Intermittent Power Supply Scheme for Sub-1 V MT-CMOS LSIs
Summary :
An experimental latch circuit is fabricated by using a 0.35µm MT-CMOS technology. This latch circuit has a volume smaller by 30%, a delay time shorter by 10%, and has an active power consumption smaller by 10% over those of a conventional MT-CMOS circuit. Furthermore, at a operation frequency of 100 MHz, an SRAM employing this IPS scheme has a standby current which is 0.4% of SRAM's without using IPS scheme.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E80-C No.12 pp.1572-1577
- Publication Date
- 1997/12/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Issue on Low-Power and High-Speed LSI Technologies)
- Category
Authors
Hironori AKAMATSU
Toru IWATA
Hiroyuki YAMAUCHI
Hisakazu KOTANI
Akira MATSUZAWA
Hiro YAMAMOTO
Takashi HIRATA
Keyword
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Hironori AKAMATSU, Toru IWATA, Hiroyuki YAMAUCHI, Hisakazu KOTANI, Akira MATSUZAWA, Hiro YAMAMOTO, Takashi HIRATA, "A Low Power Data Storage Circuit with an Intermittent Power Supply Scheme for Sub-1 V MT-CMOS LSIs" in IEICE TRANSACTIONS on Electronics,
vol. E80-C, no. 12, pp. 1572-1577, December 1997, doi: .
Abstract: An experimental latch circuit is fabricated by using a 0.35µm MT-CMOS technology. This latch circuit has a volume smaller by 30%, a delay time shorter by 10%, and has an active power consumption smaller by 10% over those of a conventional MT-CMOS circuit. Furthermore, at a operation frequency of 100 MHz, an SRAM employing this IPS scheme has a standby current which is 0.4% of SRAM's without using IPS scheme.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e80-c_12_1572/_p
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@ARTICLE{e80-c_12_1572,
author={Hironori AKAMATSU, Toru IWATA, Hiroyuki YAMAUCHI, Hisakazu KOTANI, Akira MATSUZAWA, Hiro YAMAMOTO, Takashi HIRATA, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Low Power Data Storage Circuit with an Intermittent Power Supply Scheme for Sub-1 V MT-CMOS LSIs},
year={1997},
volume={E80-C},
number={12},
pages={1572-1577},
abstract={An experimental latch circuit is fabricated by using a 0.35µm MT-CMOS technology. This latch circuit has a volume smaller by 30%, a delay time shorter by 10%, and has an active power consumption smaller by 10% over those of a conventional MT-CMOS circuit. Furthermore, at a operation frequency of 100 MHz, an SRAM employing this IPS scheme has a standby current which is 0.4% of SRAM's without using IPS scheme.},
keywords={},
doi={},
ISSN={},
month={December},}
Copy
TY - JOUR
TI - A Low Power Data Storage Circuit with an Intermittent Power Supply Scheme for Sub-1 V MT-CMOS LSIs
T2 - IEICE TRANSACTIONS on Electronics
SP - 1572
EP - 1577
AU - Hironori AKAMATSU
AU - Toru IWATA
AU - Hiroyuki YAMAUCHI
AU - Hisakazu KOTANI
AU - Akira MATSUZAWA
AU - Hiro YAMAMOTO
AU - Takashi HIRATA
PY - 1997
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E80-C
IS - 12
JA - IEICE TRANSACTIONS on Electronics
Y1 - December 1997
AB - An experimental latch circuit is fabricated by using a 0.35µm MT-CMOS technology. This latch circuit has a volume smaller by 30%, a delay time shorter by 10%, and has an active power consumption smaller by 10% over those of a conventional MT-CMOS circuit. Furthermore, at a operation frequency of 100 MHz, an SRAM employing this IPS scheme has a standby current which is 0.4% of SRAM's without using IPS scheme.
ER -
English
