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Hironori AKAMATSU Toru IWATA Hiroyuki YAMAUCHI Hisakazu KOTANI Akira MATSUZAWA Hiro YAMAMOTO Takashi HIRATA
An experimental latch circuit is fabricated by using a 0.35µm MT-CMOS technology. This latch circuit has a volume smaller by 30%, a delay time shorter by 10%, and has an active power consumption smaller by 10% over those of a conventional MT-CMOS circuit. Furthermore, at a operation frequency of 100 MHz, an SRAM employing this IPS scheme has a standby current which is 0.4% of SRAM's without using IPS scheme.