A 64-bit 100-MHz multimedia DSP core has been designed using 0.15-µ m CMOS technology. An improved Auto-Backgate-Controlled MT-CMOS (ABC-MT-CMOS) circuit with a charge pump is adopted to suppress the standby leakage current. The dynamic active current of whole chip was simulated to optimize the size of a switch for a power supply control. The DSP core chip, which integrates 300-kgate Logic, 64-kbyte SRAM and charge pump circuit, has 8-µ A standby leakage current. The reduction rate is 1/250.

An experimental latch circuit is fabricated by using a 0.35µm MT-CMOS technology. This latch circuit has a volume smaller by 30%, a delay time shorter by 10%, and has an active power consumption smaller by 10% over those of a conventional MT-CMOS circuit. Furthermore, at a operation frequency of 100 MHz, an SRAM employing this IPS scheme has a standby current which is 0.4% of SRAM's without using IPS scheme.