This paper proposes a method of constructing single-electron logic subsystems on the basis of the binary decision diagram (BDD). Sample subsystems, an adder and a comparator, are designed by combining single-electron BDD devices. It is demonstrated by computer simulation that the designed subsystems successfully produce, through pipelined processing, an output data flow in response to the input data flow. The operation error caused by thermal agitation is estimated. An output interface for converting single-electron transport into binary-voltage signals is also designed.

Area-restricted illumination of light onto a voltage-biased single-electron tunnel junction array is modeled by reduced resistance of junctions, and its effects on current-voltage characteristics, charge distributions and potential profiles are calculated by a Monte Carlo method. The results show that photocurrent nearly proportional to the applied voltage is generated above a threshold voltage determined by Coulomb blockade effect. The photocurrent increases with increasing irradiated area, which is ascribed to reduction in total resistance of the circuit. Under irradiation, a characteristic charge distribution is formed, i. e. , negative and positive charge bumps are formed in the nodes at the dark and bright boundaries. The charge bumps serve to screen the electric field formed by the bias voltage and create almost a flat potential in the irradiated area. Furthermore, time-response of the charge distribution to a pulse irradiation is also studied. For high dark resistance, the charge bumps are sustained for a long period working as a memory of light. These results suggest feasibility of single-electron photonic devices such as photodetectors and photomemories.