IEICE TRANSACTIONS on Electronics
Single-Electron Logic Systems Based on the Binary Decision Diagram
Summary :
This paper proposes a method of constructing single-electron logic subsystems on the basis of the binary decision diagram (BDD). Sample subsystems, an adder and a comparator, are designed by combining single-electron BDD devices. It is demonstrated by computer simulation that the designed subsystems successfully produce, through pipelined processing, an output data flow in response to the input data flow. The operation error caused by thermal agitation is estimated. An output interface for converting single-electron transport into binary-voltage signals is also designed.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E81-C No.1 pp.49-56
- Publication Date
- 1998/01/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Issue on Technology Challenges for Single Electron Devices)
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Noboru ASAHI, Masamichi AKAZAWA, Yoshihito AMEMIYA, "Single-Electron Logic Systems Based on the Binary Decision Diagram" in IEICE TRANSACTIONS on Electronics,
vol. E81-C, no. 1, pp. 49-56, January 1998, doi: .
Abstract: This paper proposes a method of constructing single-electron logic subsystems on the basis of the binary decision diagram (BDD). Sample subsystems, an adder and a comparator, are designed by combining single-electron BDD devices. It is demonstrated by computer simulation that the designed subsystems successfully produce, through pipelined processing, an output data flow in response to the input data flow. The operation error caused by thermal agitation is estimated. An output interface for converting single-electron transport into binary-voltage signals is also designed.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e81-c_1_49/_p
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@ARTICLE{e81-c_1_49,
author={Noboru ASAHI, Masamichi AKAZAWA, Yoshihito AMEMIYA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Single-Electron Logic Systems Based on the Binary Decision Diagram},
year={1998},
volume={E81-C},
number={1},
pages={49-56},
abstract={This paper proposes a method of constructing single-electron logic subsystems on the basis of the binary decision diagram (BDD). Sample subsystems, an adder and a comparator, are designed by combining single-electron BDD devices. It is demonstrated by computer simulation that the designed subsystems successfully produce, through pipelined processing, an output data flow in response to the input data flow. The operation error caused by thermal agitation is estimated. An output interface for converting single-electron transport into binary-voltage signals is also designed.},
keywords={},
doi={},
ISSN={},
month={January},}
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TY - JOUR
TI - Single-Electron Logic Systems Based on the Binary Decision Diagram
T2 - IEICE TRANSACTIONS on Electronics
SP - 49
EP - 56
AU - Noboru ASAHI
AU - Masamichi AKAZAWA
AU - Yoshihito AMEMIYA
PY - 1998
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E81-C
IS - 1
JA - IEICE TRANSACTIONS on Electronics
Y1 - January 1998
AB - This paper proposes a method of constructing single-electron logic subsystems on the basis of the binary decision diagram (BDD). Sample subsystems, an adder and a comparator, are designed by combining single-electron BDD devices. It is demonstrated by computer simulation that the designed subsystems successfully produce, through pipelined processing, an output data flow in response to the input data flow. The operation error caused by thermal agitation is estimated. An output interface for converting single-electron transport into binary-voltage signals is also designed.
ER -
English
