We developed a flexible-logic-gate single-electron device (SED) in which logic functions can be selected by changing the voltage applied to the control gate. It consists of an array of nanodots with multiple inputs and multiple outputs. Since the gate electrodes couple capacitively to the many dots underneath, complicated characteristics depending on the combination of the gate voltages yield a selectable logic gate when some of the gate electrodes are used as control gates. One of the important issues is how to design the arrangement of nanodots and gate electrodes. In this study, we fabricated a Si nanodot array with two simple input gates and two output terminals, in which each gate was coupled to half of the nanodot array. Even though the device had a very simple input-gate arrangement and just one control gate, we could create a half-adder function through the use of current maps as functions of the input gate voltages. We found that the nanodots evenly coupled capacitively to both input gates played an important role in getting a basic set of logic functions. Moreover, these results guarantee that a more complicated input-gate structure, in which each gate evenly couples many nanodots, will yield more complicated functions.

This paper introduces the ensemble Monte Carlo (EMC) method to study the time behavior of single-electron-based logic gates. The method is then applied to a buffer-inverter gate and the results are examined. An analytical model for time behavior at the low-temperature limit is then introduced and its results are compared with those of the EMC. Finally, a compact model for the delay-error behavior of the buffer gate is introduced.

A Recessed-Channel Dual-Gate Single Electron Transistor (RCDG-SET) which has the possibility of room temperature operation is proposed. Side gates of a RCDG-SET form electrical tunneling barriers around a recessed channel, which is newly introduced. Not only gate but also a recessed channel is self aligned to source and drain. Characteristics of a RCDG-SET are compared with those of previous DG-SETs through device simulation (SILVACO). Due to a recessed channel and a self aligned structure, MOSFET current which causes low Peak-to-Valley Current Ratio (PVCR) is suppressed. This property of a RCDG-SET is expected to contribute for room temperature operation.

This paper outlines the method of constructing single-electron logic circuits based on the binary decision diagram (BDD), a graphical representation of digital functions. The circuit consists of many unit devices, BDD devices, cascaded to build the tree of a BDD graph. Each BDD device corresponds to a node of the BDD graph and operates as a two-way switch for the transport of a single electron. Any combinatorial logic can be implemented using BDD circuits. Several subsystems for a single-electron processor have been constructed using semiconductor nano-process technology.

Single electron devices are ultra low power and extremely small devices, and suitable for implementation of large scale integrated circuits. Artificial neural networks (ANNs), which require a large number of transistors for being to be applied to practical use, is one of the possible applications of single electron devices. In order to simplify a single electron circuit configuration, we apply stochastic logic in which various complex operations can be done with basic logic gates. We design basic subcircuits of a single electron stochastic neural network, and confirm that backgate bias control and a redundant configuration are necessary for a feedback loop configuration by computer simulation based on Monte Carlo method. The proposed single electron circuit is well-suited for hardware implementation of a stochastic neural network because we can save circuit area and power consumption by using a single electron random number generator (RNG) instead of a conventional complementary metal oxide semiconductor (CMOS) RNG.

A random number generator composed of single electron devices is presented. Due to stochastic behavior of electron tunneling process, single electron devices have intrinsic randomness. Using its randomness, a true random number generator can be implemented. Although fluctuation of device parameters degrades the performance of the proposed circuit, we show that the adjustment of the bias voltages can compensate the fluctuation.

We examined the current-voltage (I-V) characteristic of metal/polyimide/rhodamine-dendorimer/polyimide/ metal junctions prepared by the Langmuir-Blodgett (LB) technique. At a temperature of 32.8 K, a step structure was observed in the I-V characteristic, whereas it was not observed for the junctions without rhodamine-dendorimer. The step structure was very similar to that seen in so-called Coulomb staircase. On the basis of the model of Coulomb blockade, the possibility of single electron tunneling via rhodamine-dendrimer (Rh-G2) molecule as a quantum dot was discussed.

We developd a method of implementing a multiple-valued Hopfield network on electronic circuits by using single-electron circuit technology. The single-electron circuit shows quantized behavior in its operation because of the discrete tunnel transport of electrons. It can therefore be successfully used for implementing neuron operation of the multiple-valued Hopfield network. The authors developed a single-electron neuron circuit that can produce the staircase transfer function required for the multiple-valued neuron. A method for constructing a multiple-valued Hopfield network by combining the neuron circuits was also developed. A sample network was designed that solves an example of the quadratic integer-programming problem. And a computer simulation demonstrated that the sample network can converge to its optimal state that represents the correct solution to the problem.

A multiple-valued logic inverter is proposed that uses single-electron-tunneling (SET) circuits in which the discreteness of the electron charge is utilized. The inverter circuit, which is composed of only two SET transistors, has a memory function as well as an inverter function for multiple-valued logic. A quantizing circuit and a D flip-flop circuit for multiple-valued logic can be compactly constructed by combining two inverters. A threshold device can be compactly constructed by attaching more than one input capacitor to the inverter circuit. A quaternary full adder circuit can be constructed by using two threshold devices. Implementation issues are also discussed.

The current-voltage characteristics of a single electron transistor (SET) in the resonant transport mode are investigated. In the future when SET devices are applied to integrated electronics, the quantum effect will seriously modify their characteristics in ultra-small geometry. The current will be dominated by the resonant transport through narrow energy levels in the dot. The simple case of a two-level system is analyzed and the transport mechanism is clarified. The transport property at low temperatures (higher than the Kondo temperature) in the low tunneling rate limit is discussed, and a current map where current values are classified in the gate bias-drain bias plane is provided. It was shown that the dynamic aspect of electron flow seriously influences the current value.

We have studied the methods to operate single electron circuits with high reliability at room temperature. By simulation, we have numerically analyzed the error mechanisms of the room-temperature operation of a 2-gate electron pump as a fundamental single electron element circuit. We have found from the results that under the room temperature condition where the ratio of the electrostatic energy to the thermal energy for a transition electron is not so large, the minimum operation error probability is obtained at the specific gate sweep time when the circuit is operated with ramp-waveform control voltages. The analyses indicate that in the shorter sweep time range, the error probability increases because the gate voltage has changed before the significant electron transition occurs, and that in the longer sweep time range, the error probability also increases due to undesired-single-transition events. The optimum sweep time is estimated statically with the relationship between desired- and undesired-single-transition rates as a function of control gate voltages. Using the optimum condition, the operation reliability is expected to be improved by a factor of 100. This estimation method has been also confirmed by the time-dependent Monte-Carlo simulation.

The basic operation characteristics of an asymmetric turnstile which transfers each electron one by one in one direction is described. A novel single electron counter circuit consisting of the asymmetric turnstiles, a load capacitor and an inverter which counts the number of high inputs is proposed. Monte Carlo circuit simulations reveal that the gate clock time of the counter circuit should be long enough to achieve allowable minimum error rate. The counter circuit implementing asymmetric single electron turnstiles is demonstrated to be applicable to a noise reduction system, a Winner-Take-All circuit and an artificial neuron circuit.

This paper proposes an architecture for circuit construction for developing single-electron integrated circuits based on majority logic. The majority logic gate circuit proposed consists of a capacitor array for input summation and a single-electron inverter for threshold operation. It accepts an odd number of inputs and produces the corresponding output on the basis of the principle of majority decision; it produces an output of logic "1" if the majority of the inputs is 1, and an output of "0" if the majority is 0. By combining the proposed majority gate circuits, various subsystems can be constructed with a smaller number of devices than that of Boolean-based construction. An adder and a parity generator are designed as examples. It is shown by computer simulation that the designed subsystems produce the correct logic operations. The operation error induced by thermal agitation is also estimated.

This paper proposes a method of constructing single-electron logic subsystems on the basis of the binary decision diagram (BDD). Sample subsystems, an adder and a comparator, are designed by combining single-electron BDD devices. It is demonstrated by computer simulation that the designed subsystems successfully produce, through pipelined processing, an output data flow in response to the input data flow. The operation error caused by thermal agitation is estimated. An output interface for converting single-electron transport into binary-voltage signals is also designed.

Gate performance for observing Coulomb oscillations and Coulomb diamonds are compared for two types of gated sub-µm double-barrier heterostructures. The first type of device contains modulation-doped barriers, whereas the second type of device contains a narrower band gap material for the well and no barriers with doped impurities. Both the Coulomb oscillations and Coulomb diamonds are modified irregularly as a function of gate voltage in the first type of device, while in the second type of device they are only systematically modified, reflecting atom-like properties of a quantum dot. This difference is explained in terms of the existence of impurities in the first type of device, which inhomogeneously deform the rotational symmetry of the lateral confining potential as the gate voltage is varied. The absence of impurities is the reason why we observe the atom-like properties only in the second type of device.

The performances of an SET required for integration are discussed. Conventional SETs had several problems such as large leakage current, insufficient voltage gain and so on. To overcome these problems, a new SET utilizing Schottky barriers as tunnel junctions is proposed. Its current characteristics and Coulomb-blockade conditions are calculated and the effectiveness for an integrated device is discussed.

New fabrication process for the nano-meter order structure was developed using the STM. The process named "STM nano-oxidation process" could oxidize the titanium metal to form the few tens of nano-meter oxidized titanium line which works as an energy barrier for the electron. The electrical properties of the TiOx line are examined in detail. The single electron transistors with back gate, or side gate, and also those with multi-islands are fabricated using STM nano-oxidation process. The single electron transistor showed the clear Coulomb gap of -160 mV, and the Coulomb oscillation with 400 mV period even at room temperature.

The edge of a thin SOI (silicon on insulator) film was used to form a very narrow Si-MOS inversion layer. The ultra-thin SOI film was formed by local oxidation of SIMOX wafer. The thickness of the SOI film is less than 15 nm, i.e., the channel width is narrower than 15 nm. At low tempera-tures, clear and large conductance oscillations were seen in this edge channel MOSFET. These oscillations are explained by Coulomb blockade effects in the narrow channel with several effective potential barriers, since the SOI film is so thin that the channel current is seriously affected by small potential fluctuations in the channel. These results suggest that the channel current in edge quantum wire MOSFET can be cut off even with a small controlled potential change. Furthermore, we fabricated a double-gate edge channel Si-MOSFET. In this device, the channel current can be controlled in two ways. One way is to control the electron number inside the isolated electrodes. The other way is to control the threshold voltage of MOSFET. This device enables us to control the phase of Coulomb oscillation.

Current status and critical issues of the material and device technology towards constructing new architecture LSIs based on quantum-mechanical principles are reviewed in an attempt to draw attention of systems workers to the field. Limitations of the present-day LSI architecture are discussed from the viewpoints of material science and device physics. New quantum mechanical phenomena in the quantum structures are reviewed. Then, key material and processing issues for fabrication of desired quantum structures are briefly discussed. Finally, the basic operation principles the quantum devices and possible architectures of quantum LSIs are discussed.