Multiple-Valued Inverter Using a Single-Electron-Tunneling Circuit

Masamichi AKAZAWA; Kentarou KANAAMI; Takashi YAMADA; Yoshihito AMEMIYA

Multiple-Valued Inverter Using a Single-Electron-Tunneling Circuit

Masamichi AKAZAWA, Kentarou KANAAMI, Takashi YAMADA, Yoshihito AMEMIYA

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A multiple-valued logic inverter is proposed that uses single-electron-tunneling (SET) circuits in which the discreteness of the electron charge is utilized. The inverter circuit, which is composed of only two SET transistors, has a memory function as well as an inverter function for multiple-valued logic. A quantizing circuit and a D flip-flop circuit for multiple-valued logic can be compactly constructed by combining two inverters. A threshold device can be compactly constructed by attaching more than one input capacitor to the inverter circuit. A quaternary full adder circuit can be constructed by using two threshold devices. Implementation issues are also discussed.

Publication: IEICE TRANSACTIONS on Electronics Vol.E82-C No.9 pp.1607-1614

Publication Date: 1999/09/25

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Type of Manuscript: Special Section PAPER (Special Issue on Integrated Electronics and New System Paradigms)

Category: Quantum Devices and Circuits

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Masamichi AKAZAWA, Kentarou KANAAMI, Takashi YAMADA, Yoshihito AMEMIYA, "Multiple-Valued Inverter Using a Single-Electron-Tunneling Circuit" in IEICE TRANSACTIONS on Electronics, vol. E82-C, no. 9, pp. 1607-1614, September 1999, doi: .
Abstract: A multiple-valued logic inverter is proposed that uses single-electron-tunneling (SET) circuits in which the discreteness of the electron charge is utilized. The inverter circuit, which is composed of only two SET transistors, has a memory function as well as an inverter function for multiple-valued logic. A quantizing circuit and a D flip-flop circuit for multiple-valued logic can be compactly constructed by combining two inverters. A threshold device can be compactly constructed by attaching more than one input capacitor to the inverter circuit. A quaternary full adder circuit can be constructed by using two threshold devices. Implementation issues are also discussed.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e82-c_9_1607/_p

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@ARTICLE{e82-c_9_1607,
author={Masamichi AKAZAWA, Kentarou KANAAMI, Takashi YAMADA, Yoshihito AMEMIYA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Multiple-Valued Inverter Using a Single-Electron-Tunneling Circuit},
year={1999},
volume={E82-C},
number={9},
pages={1607-1614},
abstract={A multiple-valued logic inverter is proposed that uses single-electron-tunneling (SET) circuits in which the discreteness of the electron charge is utilized. The inverter circuit, which is composed of only two SET transistors, has a memory function as well as an inverter function for multiple-valued logic. A quantizing circuit and a D flip-flop circuit for multiple-valued logic can be compactly constructed by combining two inverters. A threshold device can be compactly constructed by attaching more than one input capacitor to the inverter circuit. A quaternary full adder circuit can be constructed by using two threshold devices. Implementation issues are also discussed.},
keywords={},
doi={},
ISSN={},
month={September},}

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TY - JOUR
TI - Multiple-Valued Inverter Using a Single-Electron-Tunneling Circuit
T2 - IEICE TRANSACTIONS on Electronics
SP - 1607
EP - 1614
AU - Masamichi AKAZAWA
AU - Kentarou KANAAMI
AU - Takashi YAMADA
AU - Yoshihito AMEMIYA
PY - 1999
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E82-C
IS - 9
JA - IEICE TRANSACTIONS on Electronics
Y1 - September 1999
AB - A multiple-valued logic inverter is proposed that uses single-electron-tunneling (SET) circuits in which the discreteness of the electron charge is utilized. The inverter circuit, which is composed of only two SET transistors, has a memory function as well as an inverter function for multiple-valued logic. A quantizing circuit and a D flip-flop circuit for multiple-valued logic can be compactly constructed by combining two inverters. A threshold device can be compactly constructed by attaching more than one input capacitor to the inverter circuit. A quaternary full adder circuit can be constructed by using two threshold devices. Implementation issues are also discussed.
ER -