We have proposed a new SAW amplifier oscillator which has an acoustoelectric SAW amplifier and an electric feedback loop, and realized the CW oscillator experimentally. The theoretical study of the SAW oscillator has been done using the saturation characteristics of the SAW amplifier.

The carbon nanotube field-effect transistors show the hysteresis characteristic in their electrical characteristics owing to the amorphous carbon around the carbon nanotube. It is shown here the reduction of the hysteresis characteristic by the refining process applied repeatedly to the carbon nanotube. Moreover, after the refining processes, the transconductance of carbon nanotube field-effect transistor becomes 2.0 µS the ten times larger than before the refining process. Almost all carbon nanotubes without the refining processes, grown by thermal chemical vapor deposition, show the p type semiconductor characteristics. After the refining processes on the other hand, almost all carbon nanotube show the ambipolar type semiconductor characteristics.

New fabrication process for the nano-meter order structure was developed using the STM. The process named "STM nano-oxidation process" could oxidize the titanium metal to form the few tens of nano-meter oxidized titanium line which works as an energy barrier for the electron. The electrical properties of the TiOx line are examined in detail. The single electron transistors with back gate, or side gate, and also those with multi-islands are fabricated using STM nano-oxidation process. The single electron transistor showed the clear Coulomb gap of -160 mV, and the Coulomb oscillation with 400 mV period even at room temperature.

A formal verification approach that combines verification based on binary decision diagrams (BDDs) and theorem-prover-based verification has been developed. This approach is called the incremental formal verification approach. It uses an incremental verifier based on BDDs and a conventional theorem-prover-based verifier. Inputs to the incremental verifier are specifications in higher-level descriptions given in terms of arithmetic expressions, lower-level design descriptions given in terms of Boolean expressions, and constraints. The incremental verifier limits the behavior of the design by using the constraints, and compares the partial behavior limited by the constraints with the specifications by using BDD-based Boolean matching. It also replaces the matched part of the lower design description with equivalent constructs in the higher descriptions. Successive uses of the incremental verifier with different constraints can produce higher design descriptions from the lower design descriptions in a step-by-step manner. These higher descriptions are then input to the theorem-prover-based verification which enables faster treatment of larger circuits. Preliminary experimental results show that the incremental verifier can successfully check the partial equivalence and replace the matched parts by higher constructs.