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[Author] Kenji NATORI(3hit)

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  • Electrical Properties and Technological Perspectives of Thin-Film SOI MOSFETs

    Makoto YOSHIMI  Minoru TAKAHASHI  Shigeru KAMBAYASHI  Masato KEMMOCHI  Hiroaki HAZAMA  Tetsunori WADA  Koichi KATO  Hiroyuki TANGO  Kenji NATORI  

     
    INVITED PAPER

      Vol:
    E74-C No:2
      Page(s):
    337-351

    The electrical properties of thin-film SOI (silicon-on-insulator) MOSFETs, revealed by two-dimensional device simulation and experiments using electron-beam recrystallized SOI films, are reviewed and their technological perspectives are discussed. It is shown that thin-film SOI devices have a number of advantages along with some disadvantages. Carrier confinement by an interlayer SiO2 enhanced the influence of the gate electrode on the channel potential, thereby realized a high punchthrough resistance, making impurity doping into the SOI films unnecessary. The subthreshold slope factor exhibited a nearly ideal behavior, although it was somewhat degraded in the short channel region due to a two-dimensional capacitance coupling between the channel and the source or the drain. A very small capacitive-coupling between the channel and the silicon substrate made the vertical electric field extremely small, bringing about a significant increase in carrier mobility. The kink effect was confirmed to disappear due to an elevated SOI potential, which prevented impact-ionized holes from accumulating in the SOI body. The drain-current overshoot was found to be improved drastically, indicating that excess holes quickly recombine with electrons after gate turn-on, bringing about a stabilized SOI potential. However, the drain breakdown voltage had a tendency to decrease with SOI thinning, which proved to be due to an increase in the electric field at the drain. CMOS ring oscillators made with 2 µm design rule operated approximately three times faster than bulk counterparts at room temperature. It is predicted that thin-film SOI MOSFETs will have a better scalability than bulk MOSFETs not only because of their high punchthrough resistance, but because of a number of additional advantages, such as ease in device isolation as well as shallow junction formation, no impurity-induced problems, and possibility of a different scaling scenario from that in bulk devices, and so on. It is concluded that, despite some technological barries, thin-film SOI MOSFETs can offer quite a viable alternative to bulk MOSFETs as high density ULSIs, while achieving very high speed.

  • Scaling Limit of the MOS Transistor--A Ballistic MOSFET--

    Kenji NATORI  

     
    INVITED PAPER

      Vol:
    E84-C No:8
      Page(s):
    1029-1036

    The current voltage characteristics of the ballistic metal oxide semiconductor field effect transistor (MOSFET) is reviewed. Reducing the carrier scattering by employing e.g. the intrinsic channel structure and the low temperature operation, nanometer to sub-0.1 µm size MOSFETs operation approaches the ballistic transport. The drain current is derived by analyzing the carrier behavior in the vicinity of the potential maximum in the channel. The carrier degeneracy and the predominant carrier distribution in the lowest subband around the maximum point have critical effects on the current value. A convenient approximation of the current in terms of terminal voltages is given. The current control mechanism is discussed with use of the "Injection velocity," with which carriers are injected from the source to the channel. An index to represent the ballisticity is given, and some published experimental data are analyzed. Transport of the quasi-ballistic MOSFET is discussed.

  • A Compact Model for the Current-Voltage Characteristics of a Single Electron Transistor in the Resonant Transport Mode

    Kenji NATORI  Nobuyuki SANO  

     
    PAPER-Quantum Devices and Circuits

      Vol:
    E82-C No:9
      Page(s):
    1599-1606

    The current-voltage characteristics of a single electron transistor (SET) in the resonant transport mode are investigated. In the future when SET devices are applied to integrated electronics, the quantum effect will seriously modify their characteristics in ultra-small geometry. The current will be dominated by the resonant transport through narrow energy levels in the dot. The simple case of a two-level system is analyzed and the transport mechanism is clarified. The transport property at low temperatures (higher than the Kondo temperature) in the low tunneling rate limit is discussed, and a current map where current values are classified in the gate bias-drain bias plane is provided. It was shown that the dynamic aspect of electron flow seriously influences the current value.