The electrical properties of thin-film SOI (silicon-on-insulator) MOSFETs, revealed by two-dimensional device simulation and experiments using electron-beam recrystallized SOI films, are reviewed and their technological perspectives are discussed. It is shown that thin-film SOI devices have a number of advantages along with some disadvantages. Carrier confinement by an interlayer SiO2 enhanced the influence of the gate electrode on the channel potential, thereby realized a high punchthrough resistance, making impurity doping into the SOI films unnecessary. The subthreshold slope factor exhibited a nearly ideal behavior, although it was somewhat degraded in the short channel region due to a two-dimensional capacitance coupling between the channel and the source or the drain. A very small capacitive-coupling between the channel and the silicon substrate made the vertical electric field extremely small, bringing about a significant increase in carrier mobility. The kink effect was confirmed to disappear due to an elevated SOI potential, which prevented impact-ionized holes from accumulating in the SOI body. The drain-current overshoot was found to be improved drastically, indicating that excess holes quickly recombine with electrons after gate turn-on, bringing about a stabilized SOI potential. However, the drain breakdown voltage had a tendency to decrease with SOI thinning, which proved to be due to an increase in the electric field at the drain. CMOS ring oscillators made with 2 µm design rule operated approximately three times faster than bulk counterparts at room temperature. It is predicted that thin-film SOI MOSFETs will have a better scalability than bulk MOSFETs not only because of their high punchthrough resistance, but because of a number of additional advantages, such as ease in device isolation as well as shallow junction formation, no impurity-induced problems, and possibility of a different scaling scenario from that in bulk devices, and so on. It is concluded that, despite some technological barries, thin-film SOI MOSFETs can offer quite a viable alternative to bulk MOSFETs as high density ULSIs, while achieving very high speed.

A new, simple test circuit for measuring the threshold voltage distribution of flash EEPROM cell transistors is described. This circuit makes it possible to perform a reliability test for a large number of memory cell transistors with easy static operation because it reduces the measuring time drastically. In addition, this circuit can measure the highest and lowest thresh-old voltages of memory cell transistors easily. This method is suitable for performing the reliability test, such as program/erase endurance test and data retention test, for a large number of flash memory cell transistors. The usefulness of this new test circuit has been confirmed by applying it to 64 Kbit NAND-type flash memory cell array.