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Toshihiko HIMENO Naohiro MATSUKAWA Hiroaki HAZAMA Koji SAKUI Masamitsu OSHIKIRI Kazunori MASUDA Kazushige KANDA Yasuo ITOH Jin-ichi MIYAMOTO
A new, simple test circuit for measuring the threshold voltage distribution of flash EEPROM cell transistors is described. This circuit makes it possible to perform a reliability test for a large number of memory cell transistors with easy static operation because it reduces the measuring time drastically. In addition, this circuit can measure the highest and lowest thresh-old voltages of memory cell transistors easily. This method is suitable for performing the reliability test, such as program/erase endurance test and data retention test, for a large number of flash memory cell transistors. The usefulness of this new test circuit has been confirmed by applying it to 64 Kbit NAND-type flash memory cell array.