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Koichiro ISHIBASHI Tetsuya FUJIMOTO Takahiro YAMASHITA Hiroyuki OKADA Yukio ARIMA Yasuyuki HASHIMOTO Kohji SAKATA Isao MINEMATSU Yasuo ITOH Haruki TODA Motoi ICHIHASHI Yoshihide KOMATSU Masato HAGIWARA Toshiro TSUKADA
Circuit techniques for realizing low-voltage and low-power SoCs for 90-nm CMOS technology and beyond are described. A proposed SAFBB (self-adjusted forward body bias techniques), ATC (Asymmetric Three transistor Cell) DRAM, and ADC using an offset canceling comparator deal with leakage and variability issues for these technologies. A 32-bit adder using SAFBB attained 353-µA at 400-MHz operation at 0.5-V supply voltage, and 1 Mb memory array using ATC DRAM cells achieved 1.5 mA at 50 MHz, 0.5 V. The 4-bit ADC attained 2 Gsample/s operation at a supply voltage of 0.9 V.
Toshihiko HIMENO Naohiro MATSUKAWA Hiroaki HAZAMA Koji SAKUI Masamitsu OSHIKIRI Kazunori MASUDA Kazushige KANDA Yasuo ITOH Jin-ichi MIYAMOTO
A new, simple test circuit for measuring the threshold voltage distribution of flash EEPROM cell transistors is described. This circuit makes it possible to perform a reliability test for a large number of memory cell transistors with easy static operation because it reduces the measuring time drastically. In addition, this circuit can measure the highest and lowest thresh-old voltages of memory cell transistors easily. This method is suitable for performing the reliability test, such as program/erase endurance test and data retention test, for a large number of flash memory cell transistors. The usefulness of this new test circuit has been confirmed by applying it to 64 Kbit NAND-type flash memory cell array.
This letter describes the concepts that the learnability of multilayer neural networks exists in a constrained hypersurface in learning space which is formed by input and output subspace of multilayer neural networks, and that a priori information, providing constraints on the learning space, is required for generalization.
Takayuki KOBAYASHI Koji SAKUI Masaki MOMODOMI Sadayuki YOKOYAMA Yasuo ITOH Mitsugi OGURA
A new reference voltage generator for megabit DRAMs is proposed. The supply voltage dependence of the generator is successfully suppressed in comparison with the conventional reference voltage circuit. It is shown that the Vcc Margin of DRAM operation can be noticeably improved by using this generator.