IEICE TRANSACTIONS on Electronics
Low-Voltage and Low-Power Logic, Memory, and Analog Circuit Techniques for SoCs Using 90 nm Technology and Beyond
Summary :
Circuit techniques for realizing low-voltage and low-power SoCs for 90-nm CMOS technology and beyond are described. A proposed SAFBB (self-adjusted forward body bias techniques), ATC (Asymmetric Three transistor Cell) DRAM, and ADC using an offset canceling comparator deal with leakage and variability issues for these technologies. A 32-bit adder using SAFBB attained 353-µA at 400-MHz operation at 0.5-V supply voltage, and 1 Mb memory array using ATC DRAM cells achieved 1.5 mA at 50 MHz, 0.5 V. The 4-bit ADC attained 2 Gsample/s operation at a supply voltage of 0.9 V.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E89-C No.3 pp.250-262
- Publication Date
- 2006/03/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1093/ietele/e89-c.3.250
- Type of Manuscript
- Special Section INVITED PAPER (Special Section on VLSI Design Technology in the Sub-100 nm Era)
- Category
Authors
Koichiro ISHIBASHI
Tetsuya FUJIMOTO
Takahiro YAMASHITA
Hiroyuki OKADA
Yukio ARIMA
Yasuyuki HASHIMOTO
Kohji SAKATA
Isao MINEMATSU
Yasuo ITOH
Haruki TODA
Motoi ICHIHASHI
Yoshihide KOMATSU
Masato HAGIWARA
Toshiro TSUKADA
Keyword
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Koichiro ISHIBASHI, Tetsuya FUJIMOTO, Takahiro YAMASHITA, Hiroyuki OKADA, Yukio ARIMA, Yasuyuki HASHIMOTO, Kohji SAKATA, Isao MINEMATSU, Yasuo ITOH, Haruki TODA, Motoi ICHIHASHI, Yoshihide KOMATSU, Masato HAGIWARA, Toshiro TSUKADA, "Low-Voltage and Low-Power Logic, Memory, and Analog Circuit Techniques for SoCs Using 90 nm Technology and Beyond" in IEICE TRANSACTIONS on Electronics,
vol. E89-C, no. 3, pp. 250-262, March 2006, doi: 10.1093/ietele/e89-c.3.250.
Abstract: Circuit techniques for realizing low-voltage and low-power SoCs for 90-nm CMOS technology and beyond are described. A proposed SAFBB (self-adjusted forward body bias techniques), ATC (Asymmetric Three transistor Cell) DRAM, and ADC using an offset canceling comparator deal with leakage and variability issues for these technologies. A 32-bit adder using SAFBB attained 353-µA at 400-MHz operation at 0.5-V supply voltage, and 1 Mb memory array using ATC DRAM cells achieved 1.5 mA at 50 MHz, 0.5 V. The 4-bit ADC attained 2 Gsample/s operation at a supply voltage of 0.9 V.
URL: https://global.ieice.org/en_transactions/electronics/10.1093/ietele/e89-c.3.250/_p
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@ARTICLE{e89-c_3_250,
author={Koichiro ISHIBASHI, Tetsuya FUJIMOTO, Takahiro YAMASHITA, Hiroyuki OKADA, Yukio ARIMA, Yasuyuki HASHIMOTO, Kohji SAKATA, Isao MINEMATSU, Yasuo ITOH, Haruki TODA, Motoi ICHIHASHI, Yoshihide KOMATSU, Masato HAGIWARA, Toshiro TSUKADA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Low-Voltage and Low-Power Logic, Memory, and Analog Circuit Techniques for SoCs Using 90 nm Technology and Beyond},
year={2006},
volume={E89-C},
number={3},
pages={250-262},
abstract={Circuit techniques for realizing low-voltage and low-power SoCs for 90-nm CMOS technology and beyond are described. A proposed SAFBB (self-adjusted forward body bias techniques), ATC (Asymmetric Three transistor Cell) DRAM, and ADC using an offset canceling comparator deal with leakage and variability issues for these technologies. A 32-bit adder using SAFBB attained 353-µA at 400-MHz operation at 0.5-V supply voltage, and 1 Mb memory array using ATC DRAM cells achieved 1.5 mA at 50 MHz, 0.5 V. The 4-bit ADC attained 2 Gsample/s operation at a supply voltage of 0.9 V.},
keywords={},
doi={10.1093/ietele/e89-c.3.250},
ISSN={1745-1353},
month={March},}
Copy
TY - JOUR
TI - Low-Voltage and Low-Power Logic, Memory, and Analog Circuit Techniques for SoCs Using 90 nm Technology and Beyond
T2 - IEICE TRANSACTIONS on Electronics
SP - 250
EP - 262
AU - Koichiro ISHIBASHI
AU - Tetsuya FUJIMOTO
AU - Takahiro YAMASHITA
AU - Hiroyuki OKADA
AU - Yukio ARIMA
AU - Yasuyuki HASHIMOTO
AU - Kohji SAKATA
AU - Isao MINEMATSU
AU - Yasuo ITOH
AU - Haruki TODA
AU - Motoi ICHIHASHI
AU - Yoshihide KOMATSU
AU - Masato HAGIWARA
AU - Toshiro TSUKADA
PY - 2006
DO - 10.1093/ietele/e89-c.3.250
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E89-C
IS - 3
JA - IEICE TRANSACTIONS on Electronics
Y1 - March 2006
AB - Circuit techniques for realizing low-voltage and low-power SoCs for 90-nm CMOS technology and beyond are described. A proposed SAFBB (self-adjusted forward body bias techniques), ATC (Asymmetric Three transistor Cell) DRAM, and ADC using an offset canceling comparator deal with leakage and variability issues for these technologies. A 32-bit adder using SAFBB attained 353-µA at 400-MHz operation at 0.5-V supply voltage, and 1 Mb memory array using ATC DRAM cells achieved 1.5 mA at 50 MHz, 0.5 V. The 4-bit ADC attained 2 Gsample/s operation at a supply voltage of 0.9 V.
ER -
English
