This paper presents a driver status monitoring (DSM) system with body channel communication (BCC) technology to acquire the driver's physiological condition. Specifically, a conductive thread, the receiving electrode, is sewn to the surface of the seat so that the acquired signal can be continuously detected. As a signal transmission medium, body channel characteristics using the conductive thread electrode were investigated according to the driver's pose and the material of the driver's pants. Based on this, a BCC transceiver was implemented using an analog frequency modulation (FM) scheme to minimize the additional circuitry and system cost. We analyzed the heart rate variability (HRV) from the driver's electrocardiogram (ECG) and displayed the heart rate and Root Mean Square of Successive Differences (RMSSD) values together with the ECG waveform in real-time. A prototype of the DSM system with commercial-off-the-shelf (COTS) technology was implemented and tested. We verified that the proposed approach was robust to the driver's movements, showing the feasibility and validity of the DSM with BCC technology using a conductive thread electrode.

We propose a video magnification method for magnifying subtle color and motion changes under the presence of non-meaningful background motions. We use frequency variability to design a filter that passes only meaningful subtle changes and removes non-meaningful ones; our method obtains more impressive magnification results without artifacts than compared methods.

This study presents a method for improving the heartbeat interval accuracy of photoplethysmographic (PPG) sensors at ultra-low sampling rates. Although sampling rate reduction can extend battery life, it increases the sampling error and degrades the accuracy of the extracted heartbeat interval. To overcome these drawbacks, a sampling-error compensation method is proposed in this study. The sampling error is reduced by using linear interpolation and autocorrelation based on the waveform similarity of heartbeats in PPG. Furthermore, this study introduces two-line approximation and first derivative PPG (FDPPG) to improve the waveform similarity at ultra-low sampling rates. The proposed method was evaluated using measured PPG and reference electrocardiogram (ECG) of seven subjects. The results reveal that the mean absolute error (MAE) of 4.11ms was achieved for the heartbeat intervals at a sampling rate of 10Hz, compared with 1-kHz ECG sampling. The heartbeat interval error was also evaluated based on a heart rate variability (HRV) analysis. Furthermore, the mean absolute percentage error (MAPE) of the low-frequency/high-frequency (LF/HF) components obtained from the 10-Hz PPG is shown to decrease from 38.3% to 3.3%. This error is small enough for practical HRV analysis.

This paper describes a non-contact and noise-tolerant heart rate monitoring system using a 24-GHz microwave Doppler sensor. The microwave Doppler sensor placed at some distance from the user's chest detects the small vibrations of the body surface due to the heartbeats. The objective of this work is to detect the instantaneous heart rate (IHR) using this non-contact system in a car, because the possible application of the proposed system is a driver health monitoring based on heart rate variability analysis. IHR can contribute to preventing heart-triggered disasters and to detect mental stress state. However, the Doppler sensor system is very sensitive and it can be easily contaminated by motion artifacts and road noise especially while driving. To address this problem, time-frequency analysis using the parametric method and template matching method are employed. Measurement results show that the Doppler sensor, which is pasted on the clothing surface, can successfully extract the heart rate through clothes. The proposed method achieves 13.1-ms RMS error in IHR measurements conducted on 11 subjects in a car on an ordinary road.

SUMPLE, one of important signal combining approaches, its combining loss increases when a sensor in an array fails. A novel failure detection circuit for SUMPLE is proposed by using variability index. This circuit can effectively judge whether a sensor fails or not. Simulation results validate its effectiveness with respect to the existing algorithms.

In this paper, we propose a low-invasive framework to predict changes in cognitive performance using only heart rate variability (HRV). Although a lot of studies have tried to estimate cognitive performance using multiple vital data or electroencephalogram data, these methods are invasive for users because they force users to attach a lot of sensor units or electrodes to their bodies. To address this problem, we proposed a method to estimate cognitive performance using only HRV, which can be measured with as few as two electrodes. However, this can't prevent loss of worker productivity because the workers' productivity had already decreased even if their current cognitive performance had been estimated as being at a low level. In this paper, we propose a framework to predict changes in cognitive performance in the near future. We obtained three principal contributions in this paper: (1) An experiment with 45 healthy male participants clarified that changes in cognitive performance caused by mental workload can be predicted using only HRV. (2) The proposed framework, which includes a support vector machine and principal component analysis, predicts changes in cognitive performance caused by mental workload with 84.4 % accuracy. (3) Significant differences were found in some HRV features for test participants, depending on whether or not their cognitive performance changes had been predicted accurately. These results lead us to conclude that the framework has the potential to help both workers and managerial personnel predict what their performances will be in the near future. This will make it possible to proactively suggest rest periods or changes in work duties to prevent losses in productivity caused by decreases of cognitive work performance.

As the technology of VLSI manufacturing process continues to shrink, it becomes a challenging problem to generate layout patterns that can satisfy performance and manufacturability requirements. Wire width variation is one of the main issues that have a large impact on chip performance and yield loss. Particularly, etching process is the last and most influential process to wire width variation, and hence models for predicting etching induced variation have been proposed. However, they do not consider an effect of global layout variation. This work proposes a prediction model of etching induced wire width variation which takes into account global layout pattern variation. We also present a wire width adjustment method that modifies etching process on the fly according to the critical dimension loss estimated by the proposed prediction model and wire space measurement just before etching process. Experimental results show that the proposed model achieved good performance in prediction, and demonstrated that the potential reduction of the gap between the target wire width and actual wire width thanks to the proposed on-the-fly etching process modification was 68.9% on an average.

Parameter variations in nanometer process technology are one of the major design challenges. They cause delay to be increased on the critical path and may change the logic level of internal nodes. The basic concept to solve these problems at the circuit level, design-for-variability (DFV), is to add an error handling circuit to the conventional circuits so that they are robust to nanometer related variations. The state-of-the-art variation-aware flip flops are mainly evolved from aggressive dynamic voltage and frequency scaling (DVFS) -based low-power application systems which handle errors due to the scaled supply voltage. However, they only detect the timing errors and cannot correct the errors. We propose a variation-aware flip flop which can detect and correct the timing error efficiently. The experimental results show that the proposed variation-aware flip flop is more robust and lower power than the existing approaches.

Traceability links between requirements and source code are helpful in software reuse and maintenance tasks. However, manually recovering links in a large group of products requires significant costs and some links may be overlooked. Here, we propose a semi-automatic method to recover traceability links between requirements and source code in the same series of large software products. In order to support differences in representation between requirements and source code, we recover links by using the configuration management log as an intermediary. We refine the links by classifying requirements and code elements in terms of whether they are common to multiple products or specific to one. As a result of applying our method to real products that have 60KLOC, we have recovered valid traceability links within a reasonable amount of time. Automatic parts have taken 13 minutes 36 seconds, and non-automatic parts have taken about 3 hours, with a recall of 76.2% and a precision of 94.1%. Moreover, we recovered some links that were unknown to engineers. By recovering traceability links, software reusability and maintainability will be improved.

A test structure for charge-based capacitance measurement (CBCM) method has been developed to evaluate the threshold voltage variability from capacitance-voltage (C-V) curves of actual size metal-oxide-semiconductor field-effect-transistors (MOSFETs). The C-V curves from accumulation to inversion are measured for the MOSFETs having various channel dimensions using this test structure. Intrinsic capacitance components between the MOSFET electrodes are extracted from those C-V curves which are considered to include parasitic capacitance component. The intrinsic C-V curves are used for attempting to extract threshold voltage variations of their MOSFETs. It is found that the developed test structure is very useful for the evaluation of MOSFETs variability, because the derivation in MOSFET C-V curves is not influenced by current measurement noise.

The millimeter-wave band suffers strong attenuation due to rain. While calculating the link budget for a wireless system using this frequency band, the behavior of rain, attenuation due to rain, and the amount of degradation must be accurately understood. This paper presents an evaluation of the influence of rain and its attenuation on link performance in a Tokyo Institute of Technology (Tokyo Tech) millimeter-wave model mesh network. Conventional statistical analyses including cumulative rain rate distribution and specific rain attenuation constants are performed on data collected from 2009 onwards. The unique effects arising due to the highly localized behaviors of strong rainfalls have become clear and are characterized in terms of variograms rather than correlation coefficients. Spatial separation even in the small network here with links of less than 1 km provides effective diversity branches for better availability performance.

A completely-digital, on-chip performance monitor is newly proposed in this paper. In addition to a traditional ring oscillator, the proposed monitor has a special buffer chain whose output duty ratio is emphasized by the difference between NMOS and PMOS performances. Thus the performances of NMOS and PMOS transistor can accurately be estimated independently. By using only standard cells, the monitor achieves a small occupied area and process portability. To demonstrate the accuracy of performance estimation and the usability of the monitor, we have fabricated the proposed monitor using 90 nm CMOS process. The estimated errors of the drain saturation current of NMOS and PMOS transistors are 2.0% and 3.4%, respectively. A D/A converter has been also fabricated to verify the usability of the proposed monitor. The output amplitude variation of the D/A converter is successfully reduced to 50.0% by the calibration using the proposed monitor.

The self-improvement of static random access memory (SRAM) cell stability by post-fabrication high-voltage stress is experimentally demonstrated and its mechanism is analyzed using 4k device-matrix-array (DMA) SRAM test element group (TEG). It is shown that the stability of unbalance cells is automatically improved by merely applying stress voltage to the VDD terminal of SRAM. It is newly found that | VTH| of the OFF-state pFETs in the SRAM cell is selectively lowered which improves the cell stability and contributes to the self-improvement.

Distribution of current onset voltage (COV) as well as threshold voltage (VTH) and drain induced barrier lowering (DIBL) in MOSFETs fabricated by 65 nm technology is statistically analyzed. Although VTH distribution follows the normal distribution, COV and DIBL deviate from the normal distribution. It is newly found that COV follows the Gumbel distribution, which is known as one of the extreme value distributions. This result of statistical COV analysis supports our model that COV is mainly determined by the deepest potential valley between source and drain.

In this paper, negative bias temperature instability (NBTI) reliability of pFETs is analyzed under the post-fabrication SRAM self-improvement scheme that we have developed recently, where cell stability is self-improved by simply applying high stress voltage to supply voltage terminal (VDD) of SRAM cells. It is newly found that there is no significant difference in both threshold voltage and drain current degradation by NBTI stress between fresh PFETs and PFETs after self-improvement scheme application, indicating that the self-improvement scheme has no critical reliability problem.

Software product-line engineering is the successful reuse of technology when applied to component-based software development. The main concept and structure of this technology is developing reusable core assets by applying commonality and variability, and then developing new software reusing these core assets. Recently, the emergence of service-oriented environments, called SOA, has provided flexible reuse environments by reusing pre-developed component structure as service units; this is platform-independent and can integrate into heterogeneous environments. The core asset of an SOA is the service. Therefore, we can increase the reusability of an SOA by combining it with the concept of a product-line. These days, there exists research that combines SOA and product-lines, taking into account reusability. However, current research does not consider the interaction between the provider and consumer in SOA environments. Furthermore, this research tends to focus on more fragmentary aspects of product-line engineering, such as modeling and proposing variability in services. In this paper, we propose a mechanism named 2-Level SOA, including a supporting environment. This proposed mechanism deploys and manages the reusable service. In addition, by reusing and customizing this reusable service, we can develop and generate new services. Our proposed approach provides a structure to maximize the flexibility of SOA, develops services that consider systematic reuse, and constructs service-oriented applications by reusing this pre-developed reusable service. Therefore, our approach can increase both efficiency and productivity when developing service-oriented applications.

In this letter, we adopt a new factor analysis of neighborhood-preserving embedding (NPE) for speaker verification. NPE aims at preserving the local neighborhood structure on the data and defines a low-dimensional speaker space called neighborhood-preserving embedding space. We compare the proposed method with the state-of-the-art total variability approach on the telephone-telephone core condition of the NIST 2008 Speaker Recognition Evaluation (SRE) dataset. The experimental results indicate that the proposed NPE method outperforms the total variability approach, providing up to 24% relative improvement.

As MOS transistors are scaled down, the impact of randomly placed discrete charge (impurity atoms, traps and surface states) on device characteristics rapidly increases. Significant variability caused by random dopant fluctuation (RDF) is a direct result of this, which urges the adoption of new device architectures (ultra-thin body SOI FETs and FinFETs) which do not use impurity for body doping. Variability caused by traps and surface states, such as random telegraph noise (RTN), though less significant than RDF today, will soon be a major problem. The increased complexity of such residual-charge-induced variability due to non-Gaussian and time-dependent behavior will necessitate new approaches for variation-aware design.

This paper proposes an all-digital process variability monitor based on a shared structure of a buffer ring and a ring oscillator. The proposed circuit monitors the PMOS and NMOS process variabilities independently according to a count number of a single pulse which propagates on the ring during the buffer ring mode, and an oscillation period during the ring oscillator mode. Using this shared-ring structure, we reduce the occupation area about 40% without loss of process variability monitoring properties compared with the conventional circuit. The proposed shared-ring circuit has been fabricated in 65 nm CMOS process and the measurement results with two different wafer lots show the feasibility of the proposed process variability monitoring scheme.

We show measurement results of variation-tolerance of an error-hardened dual-modular-redundancy flip-flop fabricated in a 65-nm process. The proposed error-hardened FF called BCDMR is very strong against soft errors and also robust to process variations. We propose a shift-register-based test structure to measure variations. The proposed test structure has features of constant pin count and fast measurement time. A 65 nm chip was fabricated including 40k FFs to measure variations. The variations of the proposed BCDMR FF are 74% and 55% smaller than those of the conventional BISER FF on the twin-well and triple-well structures respectively.