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IEICE TRANSACTIONS on Fundamentals

Variation-Tolerance of a 65-nm Error-Hardened Dual-Modular-Redundancy Flip-Flop Measured by Shift-Register-Based Monitor Structures

Chikara HAMANAKA, Ryosuke YAMAMOTO, Jun FURUTA, Kanto KUBOTA, Kazutoshi KOBAYASHI, Hidetoshi ONODERA

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Summary :

We show measurement results of variation-tolerance of an error-hardened dual-modular-redundancy flip-flop fabricated in a 65-nm process. The proposed error-hardened FF called BCDMR is very strong against soft errors and also robust to process variations. We propose a shift-register-based test structure to measure variations. The proposed test structure has features of constant pin count and fast measurement time. A 65 nm chip was fabricated including 40k FFs to measure variations. The variations of the proposed BCDMR FF are 74% and 55% smaller than those of the conventional BISER FF on the twin-well and triple-well structures respectively.

Publication
IEICE TRANSACTIONS on Fundamentals Vol.E94-A No.12 pp.2669-2675
Publication Date
2011/12/01
Publicized
Online ISSN
1745-1337
DOI
10.1587/transfun.E94.A.2669
Type of Manuscript
Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category
High-Level Synthesis and System-Level Design

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