IEICE TRANSACTIONS on Electronics
A Standard-Cell Based On-Chip NMOS and PMOS Performance Monitor for Process Variability Compensation
Summary :
A completely-digital, on-chip performance monitor is newly proposed in this paper. In addition to a traditional ring oscillator, the proposed monitor has a special buffer chain whose output duty ratio is emphasized by the difference between NMOS and PMOS performances. Thus the performances of NMOS and PMOS transistor can accurately be estimated independently. By using only standard cells, the monitor achieves a small occupied area and process portability. To demonstrate the accuracy of performance estimation and the usability of the monitor, we have fabricated the proposed monitor using 90 nm CMOS process. The estimated errors of the drain saturation current of NMOS and PMOS transistors are 2.0% and 3.4%, respectively. A D/A converter has been also fabricated to verify the usability of the proposed monitor. The output amplitude variation of the D/A converter is successfully reduced to 50.0% by the calibration using the proposed monitor.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E96-C No.6 pp.894-902
- Publication Date
- 2013/06/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1587/transele.E96.C.894
- Type of Manuscript
- Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies)
- Category
Authors
Toshiyuki YAMAGISHI
Toshiba Corporation
Tatsuo SHIOZAWA
Toshiba Corporation
Koji HORISAKI
Toshiba Corporation
Hiroyuki HARA
Toshiba Corporation
Yasuo UNEKAWA
Toshiba Corporation
Keyword
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Toshiyuki YAMAGISHI, Tatsuo SHIOZAWA, Koji HORISAKI, Hiroyuki HARA, Yasuo UNEKAWA, "A Standard-Cell Based On-Chip NMOS and PMOS Performance Monitor for Process Variability Compensation" in IEICE TRANSACTIONS on Electronics,
vol. E96-C, no. 6, pp. 894-902, June 2013, doi: 10.1587/transele.E96.C.894.
Abstract: A completely-digital, on-chip performance monitor is newly proposed in this paper. In addition to a traditional ring oscillator, the proposed monitor has a special buffer chain whose output duty ratio is emphasized by the difference between NMOS and PMOS performances. Thus the performances of NMOS and PMOS transistor can accurately be estimated independently. By using only standard cells, the monitor achieves a small occupied area and process portability. To demonstrate the accuracy of performance estimation and the usability of the monitor, we have fabricated the proposed monitor using 90 nm CMOS process. The estimated errors of the drain saturation current of NMOS and PMOS transistors are 2.0% and 3.4%, respectively. A D/A converter has been also fabricated to verify the usability of the proposed monitor. The output amplitude variation of the D/A converter is successfully reduced to 50.0% by the calibration using the proposed monitor.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E96.C.894/_p
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@ARTICLE{e96-c_6_894,
author={Toshiyuki YAMAGISHI, Tatsuo SHIOZAWA, Koji HORISAKI, Hiroyuki HARA, Yasuo UNEKAWA, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Standard-Cell Based On-Chip NMOS and PMOS Performance Monitor for Process Variability Compensation},
year={2013},
volume={E96-C},
number={6},
pages={894-902},
abstract={A completely-digital, on-chip performance monitor is newly proposed in this paper. In addition to a traditional ring oscillator, the proposed monitor has a special buffer chain whose output duty ratio is emphasized by the difference between NMOS and PMOS performances. Thus the performances of NMOS and PMOS transistor can accurately be estimated independently. By using only standard cells, the monitor achieves a small occupied area and process portability. To demonstrate the accuracy of performance estimation and the usability of the monitor, we have fabricated the proposed monitor using 90 nm CMOS process. The estimated errors of the drain saturation current of NMOS and PMOS transistors are 2.0% and 3.4%, respectively. A D/A converter has been also fabricated to verify the usability of the proposed monitor. The output amplitude variation of the D/A converter is successfully reduced to 50.0% by the calibration using the proposed monitor.},
keywords={},
doi={10.1587/transele.E96.C.894},
ISSN={1745-1353},
month={June},}
Copy
TY - JOUR
TI - A Standard-Cell Based On-Chip NMOS and PMOS Performance Monitor for Process Variability Compensation
T2 - IEICE TRANSACTIONS on Electronics
SP - 894
EP - 902
AU - Toshiyuki YAMAGISHI
AU - Tatsuo SHIOZAWA
AU - Koji HORISAKI
AU - Hiroyuki HARA
AU - Yasuo UNEKAWA
PY - 2013
DO - 10.1587/transele.E96.C.894
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E96-C
IS - 6
JA - IEICE TRANSACTIONS on Electronics
Y1 - June 2013
AB - A completely-digital, on-chip performance monitor is newly proposed in this paper. In addition to a traditional ring oscillator, the proposed monitor has a special buffer chain whose output duty ratio is emphasized by the difference between NMOS and PMOS performances. Thus the performances of NMOS and PMOS transistor can accurately be estimated independently. By using only standard cells, the monitor achieves a small occupied area and process portability. To demonstrate the accuracy of performance estimation and the usability of the monitor, we have fabricated the proposed monitor using 90 nm CMOS process. The estimated errors of the drain saturation current of NMOS and PMOS transistors are 2.0% and 3.4%, respectively. A D/A converter has been also fabricated to verify the usability of the proposed monitor. The output amplitude variation of the D/A converter is successfully reduced to 50.0% by the calibration using the proposed monitor.
ER -
English
