IEICE TRANSACTIONS on Fundamentals
Modeling the Effect of Global Layout Pattern on Wire Width Variation for On-the-Fly Etching Process Modification
Summary :
As the technology of VLSI manufacturing process continues to shrink, it becomes a challenging problem to generate layout patterns that can satisfy performance and manufacturability requirements. Wire width variation is one of the main issues that have a large impact on chip performance and yield loss. Particularly, etching process is the last and most influential process to wire width variation, and hence models for predicting etching induced variation have been proposed. However, they do not consider an effect of global layout variation. This work proposes a prediction model of etching induced wire width variation which takes into account global layout pattern variation. We also present a wire width adjustment method that modifies etching process on the fly according to the critical dimension loss estimated by the proposed prediction model and wire space measurement just before etching process. Experimental results show that the proposed model achieved good performance in prediction, and demonstrated that the potential reduction of the gap between the target wire width and actual wire width thanks to the proposed on-the-fly etching process modification was 68.9% on an average.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E98-A No.7 pp.1467-1474
- Publication Date
- 2015/07/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1587/transfun.E98.A.1467
- Type of Manuscript
- Special Section PAPER (Special Section on Design Methodologies for System on a Chip)
- Category
Authors
Daisuke FUKUDA
Fujitsu Laboratories LTD,Osaka University
Kenichi WATANABE
Fujitsu Semiconductor LTD
Yuji KANAZAWA
Fujitsu Laboratories LTD
Masanori HASHIMOTO
Osaka University
Keyword
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Daisuke FUKUDA, Kenichi WATANABE, Yuji KANAZAWA, Masanori HASHIMOTO, "Modeling the Effect of Global Layout Pattern on Wire Width Variation for On-the-Fly Etching Process Modification" in IEICE TRANSACTIONS on Fundamentals,
vol. E98-A, no. 7, pp. 1467-1474, July 2015, doi: 10.1587/transfun.E98.A.1467.
Abstract: As the technology of VLSI manufacturing process continues to shrink, it becomes a challenging problem to generate layout patterns that can satisfy performance and manufacturability requirements. Wire width variation is one of the main issues that have a large impact on chip performance and yield loss. Particularly, etching process is the last and most influential process to wire width variation, and hence models for predicting etching induced variation have been proposed. However, they do not consider an effect of global layout variation. This work proposes a prediction model of etching induced wire width variation which takes into account global layout pattern variation. We also present a wire width adjustment method that modifies etching process on the fly according to the critical dimension loss estimated by the proposed prediction model and wire space measurement just before etching process. Experimental results show that the proposed model achieved good performance in prediction, and demonstrated that the potential reduction of the gap between the target wire width and actual wire width thanks to the proposed on-the-fly etching process modification was 68.9% on an average.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E98.A.1467/_p
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@ARTICLE{e98-a_7_1467,
author={Daisuke FUKUDA, Kenichi WATANABE, Yuji KANAZAWA, Masanori HASHIMOTO, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Modeling the Effect of Global Layout Pattern on Wire Width Variation for On-the-Fly Etching Process Modification},
year={2015},
volume={E98-A},
number={7},
pages={1467-1474},
abstract={As the technology of VLSI manufacturing process continues to shrink, it becomes a challenging problem to generate layout patterns that can satisfy performance and manufacturability requirements. Wire width variation is one of the main issues that have a large impact on chip performance and yield loss. Particularly, etching process is the last and most influential process to wire width variation, and hence models for predicting etching induced variation have been proposed. However, they do not consider an effect of global layout variation. This work proposes a prediction model of etching induced wire width variation which takes into account global layout pattern variation. We also present a wire width adjustment method that modifies etching process on the fly according to the critical dimension loss estimated by the proposed prediction model and wire space measurement just before etching process. Experimental results show that the proposed model achieved good performance in prediction, and demonstrated that the potential reduction of the gap between the target wire width and actual wire width thanks to the proposed on-the-fly etching process modification was 68.9% on an average.},
keywords={},
doi={10.1587/transfun.E98.A.1467},
ISSN={1745-1337},
month={July},}
Copy
TY - JOUR
TI - Modeling the Effect of Global Layout Pattern on Wire Width Variation for On-the-Fly Etching Process Modification
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1467
EP - 1474
AU - Daisuke FUKUDA
AU - Kenichi WATANABE
AU - Yuji KANAZAWA
AU - Masanori HASHIMOTO
PY - 2015
DO - 10.1587/transfun.E98.A.1467
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E98-A
IS - 7
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - July 2015
AB - As the technology of VLSI manufacturing process continues to shrink, it becomes a challenging problem to generate layout patterns that can satisfy performance and manufacturability requirements. Wire width variation is one of the main issues that have a large impact on chip performance and yield loss. Particularly, etching process is the last and most influential process to wire width variation, and hence models for predicting etching induced variation have been proposed. However, they do not consider an effect of global layout variation. This work proposes a prediction model of etching induced wire width variation which takes into account global layout pattern variation. We also present a wire width adjustment method that modifies etching process on the fly according to the critical dimension loss estimated by the proposed prediction model and wire space measurement just before etching process. Experimental results show that the proposed model achieved good performance in prediction, and demonstrated that the potential reduction of the gap between the target wire width and actual wire width thanks to the proposed on-the-fly etching process modification was 68.9% on an average.
ER -
English
