Cache prefetching technique brings huge benefits to performance improvement, but it comes at the cost of microarchitectural security in processors. In this letter, we deep dive into internal workings of a DCUIP prefetcher, which is one of prefetchers equipped in Intel processors. We discover that a DCUIP table is shared among different execution contexts in hyperthreading-enabled processors, which leads to another microarchitectural vulnerability. By exploiting the vulnerability, we propose a DCUIP poisoning attack. We demonstrate an AES encryption key can be extracted from an AES-NI implementation by mounting the proposed attack.

In this paper, a Proof-of-Concept (PoC) architecture is constructed, and the effectiveness of mmWave overlay heterogeneous network (HetNet) with mesh backhaul utilizing route-multiplexing and Multi-access Edge Computing (MEC) utilizing prefetching algorithm is verified by measuring the throughput and the download time of real contents. The architecture can cope with the intensive mobile data traffic since data delivery utilizes multiple backhaul routes based on the mesh topology, i.e. route-multiplexing mechanism. On the other hand, MEC deploys the network edge contents requested in advance by nearby User Equipment (UE) based on pre-registered context information such as location, destination, demand application, etc. to the network edge, which is called prefetching algorithm. Therefore, mmWave access can be fully exploited even with capacity-limited backhaul networks by introducing the proposed algorithm. These technologies solve the problems in conventional mmWave HetNet to reduce mobile data traffic on backhaul networks to cloud networks. In addition, the proposed architecture is realized by introducing wireless Software Defined Network (SDN) and Network Function Virtualization (NFV). In our architecture, the network is dynamically controlled via wide-coverage microwave band links by which UE's context information is collected for optimizing the network resources and controlling network infrastructures to establish backhaul routes and MEC servers. In this paper, we develop the hardware equipment and middleware systems, and introduce these algorithms which are used as a driver of IEEE802.11ad and open source software. For 5G and beyond, the architecture integrated in mmWave backhaul, MEC and SDN/NFV will support some scenarios and use cases.

Hardware prefetching involves a sophisticated balance between accuracy, coverage, and timeliness while minimizing hardware cost. Recent prefetchers have achieved these goals, but they still require complex hardware and a significant amount of storage. In this paper, we propose an efficient Per-page Most-Offset Prefetcher (PMOP) that minimizes hardware cost and simultaneously improves accuracy while maintaining coverage and timeliness. We achieve these objectives using an enhanced offset prefetcher that performs well with a reasonable hardware cost. Our approach first addresses coverage and timeliness by allowing multiple Most-Offset predictions. To minimize offset interference between pages, the PMOP leverages a fine-grain per-page offset filter. This filter records the access history with page-IDs, which enables efficient mapping and tracking of multiple offset streams from diverse pages. Analysis results show that PMOP outperforms the state-of-the-art Signature Path Prefetcher while reducing storage overhead by a factor of 3.4.

In this paper, we have investigated the etching selectivity of HfN encapsulating layer for high quality PtHf-alloy silicide (PtHfSi) formation with low contact resistivity on Si(100). The HfN(10 nm)/PtHf(20 nm)/p-Si(100) stacked layer was in-situ deposited by RF-magnetron sputtering at room temperature. Then, silicidation was carried out at 500°C/20 min in N2/4.9%H2 ambient. Next, the HfN encapsulating layer was etched for 1-10 min by buffered-HF (BHF) followed by the unreacted PtHf metal etching. We have found that the etching duration of the 10-nm-thick HfN encapsulating layer should be shorter than 6 min to maintain the PtHfSi crystallinity. This is probably because the PtHf-alloy silicide was gradually etched by BHF especially for the Hf atoms after the HfN was completely removed. The optimized etching process realized the ultra-low contact resistivity of PtHfSi to p+/n-Si(100) and n+/p-Si(100) such as 9.4×10-9Ωcm2 and 4.8×10-9Ωcm2, respectively, utilizing the dopant segregation process. The control of etching duration of HfN encapsulating layer is important to realize the high quality PtHfSi formation with low contact resistivity.

Dry etching is one of the elemental technologies for the fabrication of optical devices. In order to obtain the desired shape using the dry etching process, it is necessary to understand the reactivity of the materials being used to plasma. In particular, III-V compound semiconductors have a multi-layered structure comprising a plurality of elements and thus it is important to first have a full understanding of the basic trends of plasma dry etching, the plasma type and the characteristics of etching plasma sources. In this paper, III-V compound semiconductor etching for use in light sources such as LDs and LEDs, will be described. Glass, LN and LT used in the formation of waveguides and MLA will be introduced as well. And finally, the future prospects of dry etching will be described briefly.

The individual steps of UV imprint lithography have been explained in detail from the points of manufacturing nano-structures. The applications to photonic devices have been also introduced.

This paper studies the problem of recovering an arbitrarily distributed sparse matrix from its one-bit (1-bit) compressive measurements. We propose a matrix sketching based binary method iterative hard thresholding (MSBIHT) algorithm by combining the two dimensional version of BIHT (2DBIHT) and the matrix sketching method, to solve the sparse matrix recovery problem in matrix form. In contrast to traditional one-dimensional BIHT (BIHT), the proposed algorithm can reduce computational complexity. Besides, the MSBIHT can also improve the recovery performance comparing to the 2DBIHT method. A brief theoretical analysis and numerical experiments show the proposed algorithm outperforms traditional ones.

Application prefetchers improve application launch performance on HDDs through either I/O reordering or I/O interleaving, but there has been no proposal to combine the two techniques. We present a new algorithm to combine both approaches, and demonstrate that it reduces cold start launch time by 50%.

An Al-N system optical absorption layer has been developed, to be used for Al-based metal mesh electrodes on touch screen panels. The triple-layered electrode effectively suppresses the optical reflection in both visible light and the blue color region and exhibits excellent wet etching property that accommodates micro-fabrication. Due to its high noise immunity and contact sensitivity originating from its low electrical resistivity, the proposed metal mesh electrodes are useful for touch-sensitive panels in the next generation ultra-high-resolution displays.

As the technology of VLSI manufacturing process continues to shrink, it becomes a challenging problem to generate layout patterns that can satisfy performance and manufacturability requirements. Wire width variation is one of the main issues that have a large impact on chip performance and yield loss. Particularly, etching process is the last and most influential process to wire width variation, and hence models for predicting etching induced variation have been proposed. However, they do not consider an effect of global layout variation. This work proposes a prediction model of etching induced wire width variation which takes into account global layout pattern variation. We also present a wire width adjustment method that modifies etching process on the fly according to the critical dimension loss estimated by the proposed prediction model and wire space measurement just before etching process. Experimental results show that the proposed model achieved good performance in prediction, and demonstrated that the potential reduction of the gap between the target wire width and actual wire width thanks to the proposed on-the-fly etching process modification was 68.9% on an average.

We have investigated on a random-texturing process for multi-crystalline Si solar cells by plasmaless dry etching, with chlorine trifluoride (ClF3) gas treatments. The reflectance of textured surfaces was reduced to below 20% at a wavelength of 600 nm. In this study, we tried to improve the electrical characteristics by modifying the fabrication process. The substrate surfaces were dry etched by chlorine trifluoride gas and subsequently etched with an acid solution to form appropriate textured structures. The improved electrical characteristics were demonstrated.

Disk arrays and prefetching schemes are used to mitigate the performance gap between main memory and disks. This paper presents a new problem that arises if prefetching schemes that are widely used in operation systems are applied to disk arrays. The key point of the problem is that block address space from the viewpoint of the host is contiguous but from that of the disk array it is discontiguous and thus more disk accesses than expected are required. This paper presents two ways to resolve the problem that arises from the Linux readahead framework. The proposed scheme prevents a readahead window from being split into multiple requests from the viewpoint of the disk array but not from the viewpoint of the host thereby reducing disk head movements. In addition, it outperforms the prior work by adopting an asynchronous solution, improving performance for fragmented files, eliminating readahead size restriction, and improving disk parallelism. We implemented the proposed scheme and integrated it with Linux. Our experiment shows that the solution significantly improved the original Linux readahead framework when a storage server processes multiple concurrent requests.

In this paper, we report the reduction in the base-collector capacitance (CBC) of InP/InGaAs double heterojunction bipolar transistors with buried SiO2 wires (BG-HBT). In a previous trial, we could not confirm a clear difference between the CBC of the conventional HBT and that of the BG-HBT because the subcollector layer was thicker than expected. In this study, the interface between the collector and the subcollector was shifted to the middle of the SiO2 wires by adjusting the growth temperature, and a reduction in CBC with buried SiO2 wires was confirmed. The estimated CBC of the BG-HBT was 7.6 fF, while that of the conventional HBT was 8.6 fF. This 12% reduction was in agreement with the 10% reduction calculated according to the designed size.

We investigated optical transmission characteristics of aluminum thin films with periodic hole arrays in sub-wavelength. We divided white light into several color spectra using a color filter based on the surface plasmon resonance (SPR) utilizing aluminum showing high plasma frequency. By optimizing a hole-array period, hole shape, polarization and index difference of two surface, transmittance of 30% and full-width at half-maximum of around 100 nm were achieved.

This paper reports the DC and RF characteristics of AlN/GaN MOS-HEMTs passivated with thin Al2O3 formed by thermal oxidation of evaporated aluminium. Extraction of the small-signal equivalent circuit is also described. Device fabrication involved wet etching of evaporated Al from the Ohmic contact regions prior to metal deposition. This approach yielded an average contact resistance of ∼0.76 Ω.mm extracted from transmission line method (TLM) characterisation. Fabricated two-finger AlN/GaN MOS-HEMTs with 0.2 µm gate length and 100 µm gate width showed good gate control of drain currents up to a gate bias of 3 V and achieved a maximum drain current, IDSmax of ∼1460 mA/mm. The peak extrinsic transconductance, Gmax, of the device was ∼303 mS/mm at VDS = 4 V. Current-gain cut-off frequency, fT, and maximum oscillation frequency, fMAX, of 50 GHz and 40 GHz, respectively, were extracted from S-parameter measurements. For longer gate length, LG = 0.5 µm, fT and fMAX were 20 GHz and 30 GHz, respectively. These results demonstrate the potential of AlN/GaN MOS-HEMTs for high power and high frequency applications.

Designing NURBS surfaces by manipulating control points directly requires too much trial and error for immersive VR applications. A more natural interface is provided by deforming a NURBS surface so that it passes through a given target point; and by repeating such deformations we can make the surface follow one or more target curves. These deformations can be achieved by modifying the pseudo-inverse matrix of the basis functions, but this matrix is often ill-conditioned. However, the application of a modified FE approach to the weights and control points provides controllable deformations, which are demonstrated across a range of example shapes.

Conventional kernel prefetching schemes have focused on taking advantage of sequential access patterns that are easy to detect. However, it is observed that, on random and even sequential references, they may cause performance degradation due to inaccurate pattern prediction and overshooting. To address these problems, we propose a novel approach to work with existing kernel prefetching schemes, called Reference Pattern based kernel Prefetching (RPP). The RPP can reduce negative effects of existing schemes by identifying one more reference pattern, i.e., looping, in addition to random and sequential patterns and delaying starting prefetching until patterns are confirmed to be sequential or looping.

Low-power dry-etching process has been adopted to study the influence of dry-etching on Ohmic contact to p-GaN. When the surface layer of as-grown p-GaN was removed by low-power SiCl4/Cl2-etching, no Ohmic contact can be formed on the low-power dry-etched p-GaN. The same dry-etching process was also applied on n-GaN to understand the influence of the low-power dry-etching process. By capacitance-voltage (C-V) measurement, the Schottky barrier heights (SBHs) of p-GaN and n-GaN were measured. By comparing the change of measured SBHs on p-GaN and n-GaN, it was suggested that etching damage is not the only reason responsible for the degraded Ohmic contacts to dry-etched p-GaN and for Ohmic contact formatin, the original surface layer of as-grown p-GaN have some special properties, which were removed by dry-etching process. To partially recover the original surface of as-grown p-GaN, high temperature annealing (1000C 30 s) was tried on the SiCl4/Cl2-etched p-GaN and Ohmic contact was obtained.

Twin-Channel (TC)-MOSFET with twin omega-gate (Ω-gate) Si channels and its fabrication process were proposed. The twin Si channels are able to be fabricated by self-aligned process utilizing wet etching of SiN and silicon-on-insulator (SOI) wafers. Three-dimensional (3-D) device simulation was performed to optimize gate structure for TC-MOSFET with 10 nm10 nm (TSiWG) channels with the gate length of 30 nm, and it was found that TC-MOSFET with right-angled Ω-gate in case the Lunder was 3 nm showed excellent device characteristics similar to the gate-all-around (GAA) devices corresponding to the gate structure as Lunder=5 nm. Fabrication process of twin Si channels was also investigated experimentally, and approximately 40 nm40 nm twin Si channels were successfully fabricated on SOI by the proposed fabrication process.

The dry etching resistance of ArF resist patterns was improved by irradiating vacuum ultraviolet (VUV) light with a wavelength of 172 nm to ArF resist patterns in N2 atmosphere. The density of C=O bonds of the resists is decreased, and the dry etching rate of resist is also decreased after VUV irradiation. The line width shrinkage by the electron beam irradiation of CD-SEM was greatly improved from 9 nm to 2 nm, and LER (Line Edge Roughness) of resist patterns was approximately 2 nm improved from 8.4 nm to 6.5 nm under VUV irradiation. Using VUV cure, the dry etching pattern of a SiN film showed a rectangle-like cross-sectional view, and indicated almost the same LER value as the resist mask pattern. The VUV cure technique is an attractive method of fine resist pattern fabrication by ArF lithography.