In this paper we modeled and analyzed the ridge type InGaAlAs/InP semiconductor laser with lateral current confinement structure, and optimized the design for the ridge wave guide with the current confinement. We proposed and fabricated the ridge type InGaAlAs/InP laser with a cost effective selective undercut etching method and demonstrated the improvement of the ridge laser performance. This paper provides a solution to solve the cost/yield issue for conventional BH (buried hetero-structure) type laser and performance issue for conventional ridge type laser.

We have developed separation by bonding Si islands (SBSI) process for advanced CMOS LSI applications. In this process, the Si islands that become the SOI regions are formed by selective etching of the SiGe layer in the Si/SiGe stacked layers, and those are bonded to the Si substrate with the thermal oxide layers by furnace annealing. The etching selectivity for SiGe/Si and surface roughness after the SiGe etching were found to be improved by decreasing the HNO3 concentration in the etching solution. The thicknesses of the fabricated Si island and the buried oxide layer also became uniform by decreasing the HNO3 concentration. In addition, it was found that the space formed by SiGe etching in the Si/SiGe stacked layers was able to be filled with the thermal oxide layer without furnace annealing.

Buffer caching is an integral part of the operating system. In this paper, we propose a scheme that integrates buffer cache management and prefetching via cache partitioning. The scheme, which we call SA-W2R, is simple to implement, making it a feasible solution in real systems. In its basic form, for buffer replacement, it uses the LRU policy. However, its modular design allows for any replacement policy to be incorporated into the scheme. For prefetching, it uses the LRU-One Block Lookahead (LRU-OBL) approach, eliminating any extra burden that is generally necessary in other prefetching approaches. Implementation studies based on the GNU/Linux kernel version 2.2.14 show that the SA-W2R performs better than the scheme currently used, with a maximum increases of 23% for the workloads considered.

A software module for the three-dimensional simulation of etching processes has been developed. It works on multilayer structures given as triangulated surface meshes. The mesh is moved nodewise according to rates which, in this work, have been determined from isotropic and anisotropic components. An important feature of the algorithm is the automatic detection of triple lines along mask edges and the refinement of triangles at these triple lines. This allows for the simulation of underetching. The capabilities of the algorithm are demonstrated by several examples such as the simulation of glass etching for the fabrication of a phase shift mask for optical lithography and the etching of an STI trench structure. Moreover, etch profiles of a silicon substrate covered by an oxide mask are shown for different parameters of the etch components. Spacer etching has also been performed. Furthermore, a specific algorithm for the simulation of purely isotropic etching is described and demonstrated.

A parallel file system is normally used to support excessive file requests from parallel applications in a cluster system, whereas prefetching is useful for improving the file system performance. This paper proposes dynamic file prefetching scheme based on file access patterns, named table-comparison prefetching policy, that is particularly suitable for parallel scientific applications and multimedia web services in a VIA-based parallel file system. VIA relieves the communication overhead of traditional communication protocols, such as TCP/IP. The proposed policy introduces a table-comparison method to predict data for prefetching. In addition, it includes an algorithm to determine whether and when prefetching is performed using the current available I/O bandwidth. Experimental results confirmed that the use of the proposed prefetching policy in a VIA-based parallel file system produced a higher file system performance for various file access patterns.

This paper presents a high resolution long array thermal ink jet (TIJ) printhead which has been developed and demonstrated to operate successfully by combining two functional Si wafers, a bubble generating heater plate fabricated using LSI process and a channel plate fabricated using Si bulk micromachining technology. The heater plate consists of logic LSIs, high voltage MOS transistor, polycrystalline Si (Poly Si) heating resistor and polyimide protective layer. The polymide layer is patterned by O2 plasma reactive ion etching (RIE) and is applicable to high resolution heater array. The Si channel plate consists of an ink chamber and an ink inlet formed by KOH etching, and a nozzle formed by inductively coupled plasma RIE (ICP RIE). The nozzle formed by RIE has squeezed structures which contribute to high energy efficiency of drop ejector and therefore successful ejection of small ink drop. These two wafers are directly bonded by using a novel electrostatic bonding of full-cured polyimide to Si. The adhesive-less bonding provided an ideal shaped small nozzle orifice. And also, the bonding method enabled to use an on-chip LSI wafer because of the contamination free material and the suitable processing conditions (low temperature). The bonded wafer is diced to form printhead chip. No delamination or displacement of the chip was observed even though the chip was subjected to thermal stress during assembly process. This is because of no difference in thermal expansion coefficient between both chips (Si and Si). And therefore it is suitable for long chip concept. With the above technologies, we have fabricated a 1.3" long printhead with 1024 nozzles having a 800 dots per inch (dpi) resolution, a 2.7 pl. ink drop volume, 14 m/sec. ink drop velocity and 18 kHz jetting frequency. And we have confirmed high speed printing and high quality printing.

Fabrication technology for Nb integrated circuits has been developed. In developing fabrication technology, the key process steps are the etching to form fine Nb electrodes and the formation of reliable insulation layers. The standard process has been developed focusing on reproducibility and reliability. In the process, conventional reactive ion etching and RF bias-sputter deposition are used. The number of Nb wiring layers is two, and standard deviation (σ) of critical current is 0.9%, 2.3%, and 4.7% for the junction sizes of 2 µm, 1.4 µm, and 1 µm, respectively. The advanced process has also been developed focusing on capability of increasing the integration scale. Electron-cyclotron-resonance plasma etching and mechanical polishing planarization have been developed as advanced process technology. The number of Nb wiring layers is three, and σ is improved to 0.8%, 0.7%, and 1.7% for the junction sizes of 2 µm, 1.4 µm, and 1 µm, respectively. Integration limits are discussed and it is estimated that the maximum number of junctions is in the order of 105 and 107 for the standard and the advanced process, respectively. A large-scale superconducting circuit such as a several M-bit RAM can be realized in the future by using these fabrication technologies.

Prefetching is a promising approach to tackle the memory latency problem. Two basic variants of hardware data prefetching methods are sequential prefetching and stride prefetching. The latter based on stride calculation of future references has the potential to out-perform the former which is based on the data locality. In this paper, a typical stride prefetching and its improved version, adaptive stride prefetching, are compared in quantitative way using simulation for some parallel benchmark programs in the context of uniform memory access and non-uniform memory access architectures. The simulation results show that adaptability of stride is essential since the proposed adaptive scheme can reduce pending stall time which is large in the typical scheme.

To reduce the memory access latency on sharedmemory multiprocessors, several prefetching schemes have been proposed. The sequential prefetching scheme is a simple hardware-controlled scheme, which exploits the sequentiality of memory accesses to predict which blocks will be read in the near future. Aggressive sequential prefetching prefetches many blocks on each miss to reduce the miss rates and results in good performance for application programs with high sequentiality. However, conservative sequential prefetching prefetches a few blocks on each miss to avoid prefetching of useless blocks, which shows better performance than aggressive sequential prefetching for application programs with low sequentiality. We analyze the relationship between the sequentiality of application programs and the effectiveness of sequential prefetching on various memory and network latency and propose a new adaptive sequential prefetching scheme. Simply adding a small table to the sequential prefetching scheme, the proposed scheme prefetches a large number of blocks for application programs with high sequentiality and reduces the miss rates significantly, and prefetches a small number of blocks for application programs with low sequentiality and avoids loading useless blocks.

The quality of ELTRAN wafers has been improved by pre-injection in epitaxial growth, surface treatment just before bonding, high temperature annealing at bonding, high selective etching and hydrogen annealing. The pre-injection reduces defects. The surface treatment eliminates edge-voids. The high temperature bonding dramatically reduces voids all over the wafer. Hydrogen annealing is very effective for surface flattening and boron out-diffusion. In particular, the edge-void elimination by the surface treatment just before bonding is greatly effective for enlarging the SOI area and reduces the edge exclusion down to only two mm. The gate oxide integrity is well evaluated. This process promises high yield and through-put, because each of the steps can be independently optimized.

A light emitting diode (LED) array unit for use as a light source in isolated power transmission and a display panel was fabricated using LED chips mounted on a silicon microreflector. The reflector was formed on a (100) silicon wafer by anisotropic chemical etching. An isolated power supply consisting of an infrared LED array unit and single silicon crystal solar cells had a maximum transmission efficiency of 2.3%. The silicon microreflector absorbs the heat generated by the LED chips and improves their light directive characteristics. A small, high-resolution, full color LED display panel can also be constructed using LED array units fabricated on silicon microreflectors. The LEDs in a unit are arrayed with a matrix structure and the electric contacts between the LED chips, the reflector and the upper cover glass are formed using conducting silver resin.

A novel method has been developed to improve the dry etching selectivity of aluminum alloy with respect to photoresist by implanting ions into the patterned photoresist. The selectivity becomes 7.5, which is 5 times higher than that of the unimplanted case. Accordingly, this technology is very promising for fabricating multi-level interconnections in sub-half micron LSIs.

The realization of scientific manufacturing of ULSIs in the 21st century will require the development of a technical infrastructure of "Ultra Clean Technology" and the firm establishment of the three principles of high performance processes. Three principles are 1)Ultra Clean Si Wafer Surface, 2)Ultra Clean Processing Environment, and 3)Perfect Parameter controlled process. This paper describes the methods of resolving the problems inherent in Ultra Clean Technology, taking as examples issues in quarter-micron or more advanced semiconductor process and manufacturing equipment, particularly when faced with the challenges of plasma dry etching. Issues indispensable to the development of tomorrow's highly accurate and reliable plasma dry etching equipment are the development of technologies for the accurate measurement of plasma parameters, ultra clean gas delivery systems, chamber cleaning technology on an in-situ basis, and simulating the plasma chemistry.This paper also discusses the standardization of semiconductor manufacturing equipment, which is considered one of the ways to reduce the steep rise in production line construction costs. The establishment of Ultra Clean Technology also plays a vital role in this regard.

A conventional anode coupled plasma etching process has been developed to etch 300 µm-deep cavities and 600 µm-through holes with nearly vertical sidewalls into single crystal silicon. An optimized SF6/O2 gas mixture results in a nearly vertical etching profile. A silicon wafer was fabricated with a large number of cavities and through holes with less than 1 percent uniformity. It was also experimentally confirmed that this process can be used to etch vertical cavities and through holes in single-crystal silicon with any orientation. This process has the advantage of unlimited etching depth and etching patterns. Advantages in mechanical strength are obtained because a micro-curve is formed at the bottom edge of the cavities. This etching process developed on a conventional plasma etching system was utilized to fabricate a torsional vibrator that consists of single-crystal silicon and Pyrex glass.

This paper presents a new microprocessing method that uses a Cl2 fast atom beam (FAB) with stainless steel (SUS304) patterned masks. This new method uses the patterned mask instead of lithographically processed patterned photoresist materials employed in the conventional FAB microprocessing method. We examined the performance of this method by etching GaAs workpieces under various conditions: (1) by setting the distance between the mask surface and flat workpiece surface, L, from 0 µm to 500 µm; (2) by setting the angle between the FAB axis and the flat workpiece surface, θ; to either 30or 50. (3) by etching a workpiece surface that had a 15-µm step and two different surface textures, smooty and undulated; and (4) by doing overlapped etching using a square-patterned mask first and then a circular-patterned mask. The experiments show that the accuracy of reproducing the mask pattern on the etched surface increases with decreasing L. Moreover, the etching rate is almost the same (L100 µm) and decreases slightly at longer distance (L100 µm). The experiments also show that the side walls of the surface are parallel to the FAB axis, even for θ0, indicating that anisotropic etching can be achieved. The experiments for the stepped surface with different surface textures show the surface texture is not affected by the FAB etching. The overlapped etching experiments show that FAB etching is capable of producing overlapped structures. These results demonstrate that this new FAB method can be used in the microproduction of multi-faced, overlapped, three-dimensional microstructures.

Fabrication methods of novel silicon quantum wires and dots using anisotropic wet chemical etching and thermal oxidation are newly proposed. The method realizes fine Si quantum wires, which are fully surrounded by the thermal SiO2 without any defects. The wires are straight and the Si/SiO2 interfaces are fairly flat. The 10 nm width wires are confirmed by Transmitting Scanning Microscopy observation in minimum size. The fine quantum dots are also fabricated using this method. The characteristics of the wires are investigated and the current oscillations in variation with the gate voltage are observed in low temperature. We believe the origin of these oscillations arise from one-dimensional subband conduction.

The newly developed high speed DRAMs are introduced and their innovative circuit techniques for achieving a high data bandwidth are described; the synchronous DRAM, the cache DRAM and the Rambus DRAM. They are all designed to fill the performance gap between MPUs and the main memory of computer systems, which will diverge in '90s. Although these high speed DRAMs have the same purpose to increase the data bandwidth, their approaches to accomplish it is different, which may in turn lead to some advantages or disadvantages as well as their fields of applications. The paper is intended not only to discuss them from technical overview, but also to be a guide to DRAM users when choosing the best fitting one for their systems.

The progress of LSI technologies makes it possible to fabricate 256 MDRAM. However, it depends on the cost effectiveness of device fabrication that LSI memory can continue to be the technology driver or not. It is indispensable to make the device, process, and equipment as simple as possible for next generation LSI. For example, wavefront technologies in lithography, high energy ion implantation, and simple DRAM cell with SOI structure or high dielectric constant capacitor, are under development to satisfy both device performance improvement and process simplicity.

We have investigated the relationship between particle removal efficiency and etched depth in SC-1 solution (the mixture composed of ammonium hydroxide, hydrogen peroxide and DI water) for Si wafers. The Si etching rate increases with increasing NH4OH (ammonium hydroxide) concentration. The particle removal efficiency depends on the etched Si depth, and is independent of NH4OH concentration. The minimum required Si etching depth to get over 95% particle removal efficiency is 4 nm. Particles on the Si wafers exponentially decrease with increasing the etched Si depth. However the particle removal efficiency is not affected by particle size ranging from 0.2 to 0.5 µm. The particle removal mechanism on the Si wafers in SC-1 solution is dominated by the lift-off of particles due to Si undercutting and redeposition of the removed particle.

A new method for simulation of etching and deposition processes has been developed. This method is based on fundamental morphological operations derived from image and signal processing. As the material surface during simulation moves in time, the geometry either increases or decreases. If the simulation geometry is considered as a two-valued image (material or vacuum), etching and deposition processes can be simulated by means of the erosion and dilation operation. Together with a cellular material representation this method allows an accurate and stable simulation of three-dimensional arbitrary structures. Simulation results for several etching and deposition problems demonstrate accuracy and generality of our method.