A novel technique for evaluation of charge build-up in semiconductor wafer processing such as ion implantation, plasma etching and plasma enhanced chemical vapor deposition by using the breakdown of MOS capacitors with charge collecting electrodes (antenna) is proposed. The charge build-up during high beam current ion implantation is successfully evaluated by using this technique. The breakdown sensitivity of a MOS capacitor is improved by using a small area MOS capacitor with a large area antenna electrode. To estimate charge build-up on wafers quantitatively, the best combination of gate oxide thickness, substrate type, MOS capacitor area and antenna ratio should be carefully chosen for individual charge build-up situation. The optimum structured antenna MOS capacitors which relationship between QBD and stressing current density was well characterized give us very simple and quantitative charge build-up evaluation. This technique is very simple and useful to estimate charge build-up as compared with conventional technique by suing EEPROM devices or large area MOS capacitors.

We have investigated the relationship between particle removal efficiency and etched depth in SC-1 solution (the mixture composed of ammonium hydroxide, hydrogen peroxide and DI water) for Si wafers. The Si etching rate increases with increasing NH4OH (ammonium hydroxide) concentration. The particle removal efficiency depends on the etched Si depth, and is independent of NH4OH concentration. The minimum required Si etching depth to get over 95% particle removal efficiency is 4 nm. Particles on the Si wafers exponentially decrease with increasing the etched Si depth. However the particle removal efficiency is not affected by particle size ranging from 0.2 to 0.5 µm. The particle removal mechanism on the Si wafers in SC-1 solution is dominated by the lift-off of particles due to Si undercutting and redeposition of the removed particle.