A novel technique for evaluation of charge build-up in semiconductor wafer processing such as ion implantation, plasma etching and plasma enhanced chemical vapor deposition by using the breakdown of MOS capacitors with charge collecting electrodes (antenna) is proposed. The charge build-up during high beam current ion implantation is successfully evaluated by using this technique. The breakdown sensitivity of a MOS capacitor is improved by using a small area MOS capacitor with a large area antenna electrode. To estimate charge build-up on wafers quantitatively, the best combination of gate oxide thickness, substrate type, MOS capacitor area and antenna ratio should be carefully chosen for individual charge build-up situation. The optimum structured antenna MOS capacitors which relationship between QBD and stressing current density was well characterized give us very simple and quantitative charge build-up evaluation. This technique is very simple and useful to estimate charge build-up as compared with conventional technique by suing EEPROM devices or large area MOS capacitors.
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Hiroki KUBO, Takashi NAMURA, Kenji YONEDA, Hiroshi OHISHI, Yoshihiro TODOKORO, "Quantitative Charge Build-Up Evaluation Technique by Using MOS Capacitors with Charge Collecting Electrodes in Wafer Processing" in IEICE TRANSACTIONS on Electronics,
vol. E79-C, no. 2, pp. 198-205, February 1996, doi: .
Abstract: A novel technique for evaluation of charge build-up in semiconductor wafer processing such as ion implantation, plasma etching and plasma enhanced chemical vapor deposition by using the breakdown of MOS capacitors with charge collecting electrodes (antenna) is proposed. The charge build-up during high beam current ion implantation is successfully evaluated by using this technique. The breakdown sensitivity of a MOS capacitor is improved by using a small area MOS capacitor with a large area antenna electrode. To estimate charge build-up on wafers quantitatively, the best combination of gate oxide thickness, substrate type, MOS capacitor area and antenna ratio should be carefully chosen for individual charge build-up situation. The optimum structured antenna MOS capacitors which relationship between QBD and stressing current density was well characterized give us very simple and quantitative charge build-up evaluation. This technique is very simple and useful to estimate charge build-up as compared with conventional technique by suing EEPROM devices or large area MOS capacitors.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e79-c_2_198/_p
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@ARTICLE{e79-c_2_198,
author={Hiroki KUBO, Takashi NAMURA, Kenji YONEDA, Hiroshi OHISHI, Yoshihiro TODOKORO, },
journal={IEICE TRANSACTIONS on Electronics},
title={Quantitative Charge Build-Up Evaluation Technique by Using MOS Capacitors with Charge Collecting Electrodes in Wafer Processing},
year={1996},
volume={E79-C},
number={2},
pages={198-205},
abstract={A novel technique for evaluation of charge build-up in semiconductor wafer processing such as ion implantation, plasma etching and plasma enhanced chemical vapor deposition by using the breakdown of MOS capacitors with charge collecting electrodes (antenna) is proposed. The charge build-up during high beam current ion implantation is successfully evaluated by using this technique. The breakdown sensitivity of a MOS capacitor is improved by using a small area MOS capacitor with a large area antenna electrode. To estimate charge build-up on wafers quantitatively, the best combination of gate oxide thickness, substrate type, MOS capacitor area and antenna ratio should be carefully chosen for individual charge build-up situation. The optimum structured antenna MOS capacitors which relationship between QBD and stressing current density was well characterized give us very simple and quantitative charge build-up evaluation. This technique is very simple and useful to estimate charge build-up as compared with conventional technique by suing EEPROM devices or large area MOS capacitors.},
keywords={},
doi={},
ISSN={},
month={February},}
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TY - JOUR
TI - Quantitative Charge Build-Up Evaluation Technique by Using MOS Capacitors with Charge Collecting Electrodes in Wafer Processing
T2 - IEICE TRANSACTIONS on Electronics
SP - 198
EP - 205
AU - Hiroki KUBO
AU - Takashi NAMURA
AU - Kenji YONEDA
AU - Hiroshi OHISHI
AU - Yoshihiro TODOKORO
PY - 1996
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E79-C
IS - 2
JA - IEICE TRANSACTIONS on Electronics
Y1 - February 1996
AB - A novel technique for evaluation of charge build-up in semiconductor wafer processing such as ion implantation, plasma etching and plasma enhanced chemical vapor deposition by using the breakdown of MOS capacitors with charge collecting electrodes (antenna) is proposed. The charge build-up during high beam current ion implantation is successfully evaluated by using this technique. The breakdown sensitivity of a MOS capacitor is improved by using a small area MOS capacitor with a large area antenna electrode. To estimate charge build-up on wafers quantitatively, the best combination of gate oxide thickness, substrate type, MOS capacitor area and antenna ratio should be carefully chosen for individual charge build-up situation. The optimum structured antenna MOS capacitors which relationship between QBD and stressing current density was well characterized give us very simple and quantitative charge build-up evaluation. This technique is very simple and useful to estimate charge build-up as compared with conventional technique by suing EEPROM devices or large area MOS capacitors.
ER -